drivers/scsi/aic94xx/aic94xx_reg_def.h
Source file repositories/reference/linux-study-clean/drivers/scsi/aic94xx/aic94xx_reg_def.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/scsi/aic94xx/aic94xx_reg_def.h- Extension
.h- Size
- 73410 bytes
- Lines
- 2382
- Domain
- Driver Families
- Bucket
- drivers/scsi
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _ADP94XX_REG_DEF_H_
#define _ADP94XX_REG_DEF_H_
/*
* Common definitions.
*/
#define CSEQ_MODE_PAGE_SIZE 0x200 /* CSEQ mode page size */
#define LmSEQ_MODE_PAGE_SIZE 0x200 /* LmSEQ mode page size */
#define LmSEQ_HOST_REG_SIZE 0x4000 /* LmSEQ Host Register size */
/********************* COM_SAS registers definition *************************/
/* The base is REG_BASE_ADDR, defined in aic94xx_reg.h.
*/
/*
* CHIM Registers, Address Range : (0x00-0xFF)
*/
#define COMBIST (REG_BASE_ADDR + 0x00)
/* bits 31:24 */
#define L7BLKRST 0x80000000
#define L6BLKRST 0x40000000
#define L5BLKRST 0x20000000
#define L4BLKRST 0x10000000
#define L3BLKRST 0x08000000
#define L2BLKRST 0x04000000
#define L1BLKRST 0x02000000
#define L0BLKRST 0x01000000
#define LmBLKRST 0xFF000000
#define LmBLKRST_COMBIST(phyid) (1 << (24 + phyid))
#define OCMBLKRST 0x00400000
#define CTXMEMBLKRST 0x00200000
#define CSEQBLKRST 0x00100000
#define EXSIBLKRST 0x00040000
#define DPIBLKRST 0x00020000
#define DFIFBLKRST 0x00010000
#define HARDRST 0x00000200
#define COMBLKRST 0x00000100
#define FRCDFPERR 0x00000080
#define FRCCIOPERR 0x00000020
#define FRCBISTERR 0x00000010
#define COMBISTEN 0x00000004
#define COMBISTDONE 0x00000002 /* ro */
#define COMBISTFAIL 0x00000001 /* ro */
#define COMSTAT (REG_BASE_ADDR + 0x04)
#define REQMBXREAD 0x00000040
#define RSPMBXAVAIL 0x00000020
#define CSBUFPERR 0x00000008
#define OVLYERR 0x00000004
#define CSERR 0x00000002
#define OVLYDMADONE 0x00000001
#define COMSTAT_MASK (REQMBXREAD | RSPMBXAVAIL | \
CSBUFPERR | OVLYERR | CSERR |\
OVLYDMADONE)
#define COMSTATEN (REG_BASE_ADDR + 0x08)
#define EN_REQMBXREAD 0x00000040
#define EN_RSPMBXAVAIL 0x00000020
#define EN_CSBUFPERR 0x00000008
#define EN_OVLYERR 0x00000004
#define EN_CSERR 0x00000002
#define EN_OVLYDONE 0x00000001
#define SCBPRO (REG_BASE_ADDR + 0x0C)
#define SCBCONS_MASK 0xFFFF0000
#define SCBPRO_MASK 0x0000FFFF
#define CHIMREQMBX (REG_BASE_ADDR + 0x10)
#define CHIMRSPMBX (REG_BASE_ADDR + 0x14)
#define CHIMINT (REG_BASE_ADDR + 0x18)
#define EXT_INT0 0x00000800
#define EXT_INT1 0x00000400
#define PORRSTDET 0x00000200
#define HARDRSTDET 0x00000100
#define DLAVAILQ 0x00000080 /* ro */
#define HOSTERR 0x00000040
#define INITERR 0x00000020
#define DEVINT 0x00000010
#define COMINT 0x00000008
#define DEVTIMER2 0x00000004
Annotation
- Atlas domain: Driver Families / drivers/scsi.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.