drivers/scsi/aic94xx/aic94xx_reg.h
Source file repositories/reference/linux-study-clean/drivers/scsi/aic94xx/aic94xx_reg.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/scsi/aic94xx/aic94xx_reg.h- Extension
.h- Size
- 9734 bytes
- Lines
- 285
- Domain
- Driver Families
- Bucket
- drivers/scsi
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
asm/io.haic94xx_hwi.haic94xx_reg_def.h
Detected Declarations
function asd_ddbsite_read_bytefunction asd_ddbsite_write_bytefunction asd_scbsite_read_bytefunction asd_scbsite_write_bytefunction asd_ddbsite_update_wordfunction asd_ddbsite_update_bytefunction asd_write_reg_addrfunction asd_get_cmdctx_sizefunction asd_get_devctx_sizefunction asd_disable_intsfunction asd_enable_ints
Annotated Snippet
#ifndef _AIC94XX_REG_H_
#define _AIC94XX_REG_H_
#include <asm/io.h>
#include "aic94xx_hwi.h"
/* Values */
#define AIC9410_DEV_REV_B0 0x8
/* MBAR0, SWA, SWB, SWC, internal memory space addresses */
#define REG_BASE_ADDR 0xB8000000
#define REG_BASE_ADDR_CSEQCIO 0xB8002000
#define REG_BASE_ADDR_EXSI 0xB8042800
#define MBAR0_SWA_SIZE 0x58
extern u32 MBAR0_SWB_SIZE;
#define MBAR0_SWC_SIZE 0x8
/* MBAR1, points to On Chip Memory */
#define OCM_BASE_ADDR 0xA0000000
#define OCM_MAX_SIZE 0x20000
/* Smallest address possible to reference */
#define ALL_BASE_ADDR OCM_BASE_ADDR
/* PCI configuration space registers */
#define PCI_IOBAR_OFFSET 4
#define PCI_CONF_MBAR1 0x6C
#define PCI_CONF_MBAR0_SWA 0x70
#define PCI_CONF_MBAR0_SWB 0x74
#define PCI_CONF_MBAR0_SWC 0x78
#define PCI_CONF_MBAR_KEY 0x7C
#define PCI_CONF_FLSH_BAR 0xB8
#include "aic94xx_reg_def.h"
u8 asd_read_reg_byte(struct asd_ha_struct *asd_ha, u32 reg);
u16 asd_read_reg_word(struct asd_ha_struct *asd_ha, u32 reg);
u32 asd_read_reg_dword(struct asd_ha_struct *asd_ha, u32 reg);
void asd_write_reg_byte(struct asd_ha_struct *asd_ha, u32 reg, u8 val);
void asd_write_reg_word(struct asd_ha_struct *asd_ha, u32 reg, u16 val);
void asd_write_reg_dword(struct asd_ha_struct *asd_ha, u32 reg, u32 val);
void asd_read_reg_string(struct asd_ha_struct *asd_ha, void *dst,
u32 offs, int count);
void asd_write_reg_string(struct asd_ha_struct *asd_ha, void *src,
u32 offs, int count);
#define ASD_READ_OCM(type, ord, S) \
static inline type asd_read_ocm_##ord (struct asd_ha_struct *asd_ha, \
u32 offs) \
{ \
struct asd_ha_addrspace *io_handle = &asd_ha->io_handle[1]; \
type val = read##S (io_handle->addr + (unsigned long) offs); \
rmb(); \
return val; \
}
ASD_READ_OCM(u8, byte, b);
ASD_READ_OCM(u16,word, w);
ASD_READ_OCM(u32,dword,l);
#define ASD_WRITE_OCM(type, ord, S) \
static inline void asd_write_ocm_##ord (struct asd_ha_struct *asd_ha, \
u32 offs, type val) \
{ \
struct asd_ha_addrspace *io_handle = &asd_ha->io_handle[1]; \
write##S (val, io_handle->addr + (unsigned long) offs); \
return; \
}
ASD_WRITE_OCM(u8, byte, b);
ASD_WRITE_OCM(u16,word, w);
ASD_WRITE_OCM(u32,dword,l);
#define ASD_DDBSITE_READ(type, ord) \
static inline type asd_ddbsite_read_##ord (struct asd_ha_struct *asd_ha, \
u16 ddb_site_no, \
u16 offs) \
{ \
asd_write_reg_word(asd_ha, ALTCIOADR, MnDDB_SITE + offs); \
asd_write_reg_word(asd_ha, ADDBPTR, ddb_site_no); \
return asd_read_reg_##ord (asd_ha, CTXACCESS); \
}
ASD_DDBSITE_READ(u32, dword);
ASD_DDBSITE_READ(u16, word);
Annotation
- Immediate include surface: `asm/io.h`, `aic94xx_hwi.h`, `aic94xx_reg_def.h`.
- Detected declarations: `function asd_ddbsite_read_byte`, `function asd_ddbsite_write_byte`, `function asd_scbsite_read_byte`, `function asd_scbsite_write_byte`, `function asd_ddbsite_update_word`, `function asd_ddbsite_update_byte`, `function asd_write_reg_addr`, `function asd_get_cmdctx_size`, `function asd_get_devctx_size`, `function asd_disable_ints`.
- Atlas domain: Driver Families / drivers/scsi.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.