drivers/scsi/be2iscsi/be_cmds.h

Source file repositories/reference/linux-study-clean/drivers/scsi/be2iscsi/be_cmds.h

File Facts

System
Linux kernel
Corpus path
drivers/scsi/be2iscsi/be_cmds.h
Extension
.h
Size
38192 bytes
Lines
1462
Domain
Driver Families
Bucket
drivers/scsi
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct be_sge {
	__le32 pa_lo;
	__le32 pa_hi;
	__le32 len;
};

struct be_mcc_wrb {
	u32 emb_sgecnt_special;	/* dword 0 */
	/* bits 0 - embedded    */
	/* bits 1 - 2 reserved	*/
	/* bits 3 - 7 sge count	*/
	/* bits 8 - 23 reserved	*/
	/* bits 24 - 31 special	*/
#define MCC_WRB_EMBEDDED_MASK 1
#define MCC_WRB_SGE_CNT_SHIFT 3
#define MCC_WRB_SGE_CNT_MASK 0x1F
	u32 payload_length;	/* dword 1 */
	u32 tag0;		/* dword 2 */
	u32 tag1;		/* dword 3 */
	u32 rsvd;		/* dword 4 */
	union {
#define EMBED_MBX_MAX_PAYLOAD_SIZE  220
		u8 embedded_payload[236];	/* used by embedded cmds */
		struct be_sge sgl[19];	/* used by non-embedded cmds */
	} payload;
};

#define CQE_FLAGS_VALID_MASK (1 << 31)
#define CQE_FLAGS_ASYNC_MASK (1 << 30)
#define CQE_FLAGS_COMPLETED_MASK	(1 << 28)
#define CQE_FLAGS_CONSUMED_MASK		(1 << 27)

/* Completion Status */
#define MCC_STATUS_SUCCESS 0x0
#define MCC_STATUS_FAILED 0x1
#define MCC_STATUS_ILLEGAL_REQUEST 0x2
#define MCC_STATUS_ILLEGAL_FIELD 0x3
#define MCC_STATUS_INSUFFICIENT_BUFFER 0x4
#define MCC_STATUS_INVALID_LENGTH 0x74

#define CQE_STATUS_COMPL_MASK	0xFFFF
#define CQE_STATUS_COMPL_SHIFT	0		/* bits 0 - 15 */
#define CQE_STATUS_EXTD_MASK	0xFFFF
#define CQE_STATUS_EXTD_SHIFT	16		/* bits 31 - 16 */
#define CQE_STATUS_ADDL_MASK	0xFF00
#define CQE_STATUS_ADDL_SHIFT	8
#define CQE_STATUS_MASK		0xFF
#define CQE_STATUS_WRB_MASK	0xFF0000
#define CQE_STATUS_WRB_SHIFT	16

#define BEISCSI_HOST_MBX_TIMEOUT (110 * 1000)
#define BEISCSI_FW_MBX_TIMEOUT	100

/* MBOX Command VER */
#define MBX_CMD_VER1	0x01
#define MBX_CMD_VER2	0x02

struct be_mcc_compl {
	u32 status;		/* dword 0 */
	u32 tag0;		/* dword 1 */
	u32 tag1;		/* dword 2 */
	u32 flags;		/* dword 3 */
};

/********* Mailbox door bell *************/
/**
 * Used for driver communication with the FW.
 * The software must write this register twice to post any command. First,
 * it writes the register with hi=1 and the upper bits of the physical address
 * for the MAILBOX structure. Software must poll the ready bit until this
 * is acknowledged. Then, sotware writes the register with hi=0 with the lower
 * bits in the address. It must poll the ready bit until the command is
 * complete. Upon completion, the MAILBOX will contain a valid completion
 * queue entry.
 */
#define MPU_MAILBOX_DB_OFFSET	0x160
#define MPU_MAILBOX_DB_RDY_MASK	0x1	/* bit 0 */
#define MPU_MAILBOX_DB_HI_MASK	0x2	/* bit 1 */

/********** MPU semphore: used for SH & BE ******************/
#define SLIPORT_SOFTRESET_OFFSET		0x5c	/* CSR BAR offset */
#define SLIPORT_SEMAPHORE_OFFSET_BEx		0xac	/* CSR BAR offset */
#define SLIPORT_SEMAPHORE_OFFSET_SH		0x94	/* PCI-CFG offset */
#define POST_STAGE_MASK				0x0000FFFF
#define POST_ERROR_BIT				0x80000000
#define POST_ERR_RECOVERY_CODE_MASK		0xF000

/* Soft Reset register masks */
#define SLIPORT_SOFTRESET_SR_MASK		0x00000080	/* SR bit */

Annotation

Implementation Notes