drivers/scsi/bfa/bfa_hw_ct.c
Source file repositories/reference/linux-study-clean/drivers/scsi/bfa/bfa_hw_ct.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/scsi/bfa/bfa_hw_ct.c- Extension
.c- Size
- 3763 bytes
- Lines
- 170
- Domain
- Driver Families
- Bucket
- drivers/scsi
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
bfad_drv.hbfa_modules.hbfi_reg.h
Detected Declarations
function bfa_hwct_msix_dummyfunction bfa_hwct2_reginitfunction bfa_hwct_reqq_ackfunction bfa_hwct_rspq_ackfunction bfa_hwct2_rspq_ackfunction bfa_hwct_msix_getvecsfunction bfa_hwct_msix_initfunction bfa_hwct_msix_ctrl_installfunction bfa_hwct_msix_queue_installfunction bfa_hwct_msix_uninstallfunction bfa_hwct_isr_mode_setfunction bfa_hwct_msix_get_rme_range
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
* Copyright (c) 2014- QLogic Corporation.
* All rights reserved
* www.qlogic.com
*
* Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
*/
#include "bfad_drv.h"
#include "bfa_modules.h"
#include "bfi_reg.h"
BFA_TRC_FILE(HAL, IOCFC_CT);
/*
* Dummy interrupt handler for handling spurious interrupt during chip-reinit.
*/
static void
bfa_hwct_msix_dummy(struct bfa_s *bfa, int vec)
{
}
void
bfa_hwct_reginit(struct bfa_s *bfa)
{
struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
int fn = bfa_ioc_pcifn(&bfa->ioc);
if (fn == 0) {
bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK);
} else {
bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK);
}
}
void
bfa_hwct2_reginit(struct bfa_s *bfa)
{
struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
bfa_regs->intr_status = (kva + CT2_HOSTFN_INT_STATUS);
bfa_regs->intr_mask = (kva + CT2_HOSTFN_INTR_MASK);
}
void
bfa_hwct_reqq_ack(struct bfa_s *bfa, int reqq)
{
u32 r32;
r32 = readl(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
writel(r32, bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
}
/*
* Actions to respond RME Interrupt for Catapult ASIC:
* - Write 1 to Interrupt Status register (INTx only - done in bfa_intx())
* - Acknowledge by writing to RME Queue Control register
* - Update CI
*/
void
bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci)
{
u32 r32;
r32 = readl(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
writel(r32, bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
bfa_rspq_ci(bfa, rspq) = ci;
writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
}
/*
* Actions to respond RME Interrupt for Catapult2 ASIC:
* - Write 1 to Interrupt Status register (INTx only - done in bfa_intx())
* - Update CI
*/
void
bfa_hwct2_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci)
{
bfa_rspq_ci(bfa, rspq) = ci;
writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
}
void
Annotation
- Immediate include surface: `bfad_drv.h`, `bfa_modules.h`, `bfi_reg.h`.
- Detected declarations: `function bfa_hwct_msix_dummy`, `function bfa_hwct2_reginit`, `function bfa_hwct_reqq_ack`, `function bfa_hwct_rspq_ack`, `function bfa_hwct2_rspq_ack`, `function bfa_hwct_msix_getvecs`, `function bfa_hwct_msix_init`, `function bfa_hwct_msix_ctrl_install`, `function bfa_hwct_msix_queue_install`, `function bfa_hwct_msix_uninstall`.
- Atlas domain: Driver Families / drivers/scsi.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.