drivers/scsi/bfa/bfi_ms.h

Source file repositories/reference/linux-study-clean/drivers/scsi/bfa/bfi_ms.h

File Facts

System
Linux kernel
Corpus path
drivers/scsi/bfa/bfi_ms.h
Extension
.h
Size
22106 bytes
Lines
872
Domain
Driver Families
Bucket
drivers/scsi
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct bfi_iocfc_cfg_s {
	u8	num_cqs;	/*  Number of CQs to be used	*/
	u8	 sense_buf_len;	/*  SCSI sense length	    */
	u16	rsvd_1;
	u32	endian_sig;	/*  endian signature of host     */
	u8	rsvd_2;
	u8	single_msix_vec;
	u8	rsvd[2];
	__be16	num_ioim_reqs;
	__be16	num_fwtio_reqs;


	/*
	 * Request and response circular queue base addresses, size and
	 * shadow index pointers.
	 */
	union bfi_addr_u  req_cq_ba[BFI_IOC_MAX_CQS];
	union bfi_addr_u  req_shadow_ci[BFI_IOC_MAX_CQS];
	__be16    req_cq_elems[BFI_IOC_MAX_CQS];
	union bfi_addr_u  rsp_cq_ba[BFI_IOC_MAX_CQS];
	union bfi_addr_u  rsp_shadow_pi[BFI_IOC_MAX_CQS];
	__be16    rsp_cq_elems[BFI_IOC_MAX_CQS];

	union bfi_addr_u  stats_addr;	/*  DMA-able address for stats	  */
	union bfi_addr_u  cfgrsp_addr;	/*  config response dma address  */
	union bfi_addr_u  ioim_snsbase[BFI_IOIM_SNSBUF_SEGS];
					/*  IO sense buf base addr segments */
	struct bfa_iocfc_intr_attr_s intr_attr; /*  IOC interrupt attributes */
};

/*
 * Boot target wwn information for this port. This contains either the stored
 * or discovered boot target port wwns for the port.
 */
struct bfi_iocfc_bootwwns {
	wwn_t		wwn[BFA_BOOT_BOOTLUN_MAX];
	u8		nwwns;
	u8		rsvd[7];
};

/**
 * Queue configuration response from firmware
 */
struct bfi_iocfc_qreg_s {
	u32	cpe_q_ci_off[BFI_IOC_MAX_CQS];
	u32	cpe_q_pi_off[BFI_IOC_MAX_CQS];
	u32	cpe_qctl_off[BFI_IOC_MAX_CQS];
	u32	rme_q_ci_off[BFI_IOC_MAX_CQS];
	u32	rme_q_pi_off[BFI_IOC_MAX_CQS];
	u32	rme_qctl_off[BFI_IOC_MAX_CQS];
	u8	hw_qid[BFI_IOC_MAX_CQS];
};

struct bfi_iocfc_cfgrsp_s {
	struct bfa_iocfc_fwcfg_s	fwcfg;
	struct bfa_iocfc_intr_attr_s	intr_attr;
	struct bfi_iocfc_bootwwns	bootwwns;
	struct bfi_pbc_s		pbc_cfg;
	struct bfi_iocfc_qreg_s		qreg;
};

/*
 * BFI_IOCFC_H2I_CFG_REQ message
 */
struct bfi_iocfc_cfg_req_s {
	struct bfi_mhdr_s      mh;
	union bfi_addr_u      ioc_cfg_dma_addr;
};


/*
 * BFI_IOCFC_I2H_CFG_REPLY message
 */
struct bfi_iocfc_cfg_reply_s {
	struct bfi_mhdr_s  mh;		/*  Common msg header	  */
	u8	 cfg_success;	/*  cfg reply status	   */
	u8	 lpu_bm;		/*  LPUs assigned for this IOC */
	u8	 rsvd[2];
};


/*
 * BFI_IOCFC_H2I_SET_INTR_REQ message
 */
struct bfi_iocfc_set_intr_req_s {
	struct bfi_mhdr_s mh;		/*  common msg header		*/
	u8		coalesce;	/*  enable intr coalescing	*/
	u8		rsvd[3];
	__be16	delay;		/*  delay timer 0..1125us	*/
	__be16	latency;	/*  latency timer 0..225us	*/

Annotation

Implementation Notes