drivers/scsi/csiostor/csio_hw_t5.c
Source file repositories/reference/linux-study-clean/drivers/scsi/csiostor/csio_hw_t5.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/scsi/csiostor/csio_hw_t5.c- Extension
.c- Size
- 13003 bytes
- Lines
- 370
- Domain
- Driver Families
- Bucket
- drivers/scsi
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
csio_hw.hcsio_init.h
Detected Declarations
function Copyrightfunction csio_t5_pcie_intr_handlerfunction csio_t5_flash_cfg_addrfunction csio_t5_mc_readfunction csio_t5_edc_readfunction csio_t5_memory_rwfunction csio_t5_dfs_create_ext_mem
Annotated Snippet
while (offset < mem_aperture && len > 0) {
if (dir)
*buf++ = csio_rd_reg32(hw, mem_base + offset);
else
csio_wr_reg32(hw, *buf++, mem_base + offset);
offset += sizeof(__be32);
len -= sizeof(__be32);
}
}
return 0;
}
/*
* csio_t5_dfs_create_ext_mem - setup debugfs for MC0 or MC1 to read the values
* @hw: the csio_hw
*
* This function creates files in the debugfs with external memory region
* MC0 & MC1.
*/
static void
csio_t5_dfs_create_ext_mem(struct csio_hw *hw)
{
u32 size;
int i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE_A);
if (i & EXT_MEM_ENABLE_F) {
size = csio_rd_reg32(hw, MA_EXT_MEMORY_BAR_A);
csio_add_debugfs_mem(hw, "mc0", MEM_MC0,
EXT_MEM_SIZE_G(size));
}
if (i & EXT_MEM1_ENABLE_F) {
size = csio_rd_reg32(hw, MA_EXT_MEMORY1_BAR_A);
csio_add_debugfs_mem(hw, "mc1", MEM_MC1,
EXT_MEM_SIZE_G(size));
}
}
/* T5 adapter specific function */
struct csio_hw_chip_ops t5_ops = {
.chip_set_mem_win = csio_t5_set_mem_win,
.chip_pcie_intr_handler = csio_t5_pcie_intr_handler,
.chip_flash_cfg_addr = csio_t5_flash_cfg_addr,
.chip_mc_read = csio_t5_mc_read,
.chip_edc_read = csio_t5_edc_read,
.chip_memory_rw = csio_t5_memory_rw,
.chip_dfs_create_ext_mem = csio_t5_dfs_create_ext_mem,
};
Annotation
- Immediate include surface: `csio_hw.h`, `csio_init.h`.
- Detected declarations: `function Copyright`, `function csio_t5_pcie_intr_handler`, `function csio_t5_flash_cfg_addr`, `function csio_t5_mc_read`, `function csio_t5_edc_read`, `function csio_t5_memory_rw`, `function csio_t5_dfs_create_ext_mem`.
- Atlas domain: Driver Families / drivers/scsi.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.