drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

File Facts

System

Linux kernel

Corpus path

drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

Extension

.c

Size

108942 bytes

Lines

3668

Domain

Driver Families

Bucket

drivers/scsi

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• hisi_sas.h

Detected Declarations

• struct hisi_sas_complete_v2_hdr
• struct hisi_sas_err_record_v2
• struct signal_attenuation_s
• struct sig_atten_lu_s
• function hisi_sas_read32
• function hisi_sas_read32_relaxed
• function hisi_sas_write32
• function hisi_sas_phy_write32
• function hisi_sas_phy_read32
• function slot_index_alloc_quirk_v2_hw
• function sata_index_alloc_v2_hw
• function config_phy_opt_mode_v2_hw
• function config_id_frame_v2_hw
• function setup_itct_v2_hw
• function clear_itct_v2_hw
• function free_device_v2_hw
• function reset_hw_v2_hw
• function phys_reject_stp_links_v2_hw
• function phys_try_accept_stp_links_v2_hw
• function init_reg_v2_hw
• function link_timeout_enable_link
• function link_timeout_disable_link
• function set_link_timer_quirk
• function hw_init_v2_hw
• function enable_phy_v2_hw
• function is_sata_phy_v2_hw
• function tx_fifo_is_empty_v2_hw
• function axi_bus_is_idle_v2_hw
• function wait_io_done_v2_hw
• function allowed_disable_phy_v2_hw
• function disable_phy_v2_hw
• function start_phy_v2_hw
• function phy_hard_reset_v2_hw
• function phy_get_events_v2_hw
• function phys_init_v2_hw
• function sl_notify_ssp_v2_hw
• function phy_get_max_linkrate_v2_hw
• function phy_set_linkrate_v2_hw
• function get_wideport_bitmap_v2_hw
• function start_delivery_v2_hw
• function list_for_each_entry_safe
• function prep_prd_sge_v2_hw
• function for_each_sg
• function prep_smp_v2_hw
• function prep_ssp_v2_hw
• function parse_trans_tx_err_code_v2_hw
• function parse_trans_rx_err_code_v2_hw
• function parse_dma_tx_err_code_v2_hw

Annotated Snippet

struct hisi_sas_complete_v2_hdr {
	__le32 dw0;
	__le32 dw1;
	__le32 act;
	__le32 dw3;
};

struct hisi_sas_err_record_v2 {
	/* dw0 */
	__le32 trans_tx_fail_type;

	/* dw1 */
	__le32 trans_rx_fail_type;

	/* dw2 */
	__le16 dma_tx_err_type;
	__le16 sipc_rx_err_type;

	/* dw3 */
	__le32 dma_rx_err_type;
};

struct signal_attenuation_s {
	u32 de_emphasis;
	u32 preshoot;
	u32 boost;
};

struct sig_atten_lu_s {
	const struct signal_attenuation_s *att;
	u32 sas_phy_ctrl;
};

static const struct hisi_sas_hw_error one_bit_ecc_errors[] = {
	{
		.irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_1B_OFF),
		.msk = HGC_DQE_ECC_1B_ADDR_MSK,
		.shift = HGC_DQE_ECC_1B_ADDR_OFF,
		.msg = "hgc_dqe_ecc1b_intr",
		.reg = HGC_DQE_ECC_ADDR,
	},
	{
		.irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_1B_OFF),
		.msk = HGC_IOST_ECC_1B_ADDR_MSK,
		.shift = HGC_IOST_ECC_1B_ADDR_OFF,
		.msg = "hgc_iost_ecc1b_intr",
		.reg = HGC_IOST_ECC_ADDR,
	},
	{
		.irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_1B_OFF),
		.msk = HGC_ITCT_ECC_1B_ADDR_MSK,
		.shift = HGC_ITCT_ECC_1B_ADDR_OFF,
		.msg = "hgc_itct_ecc1b_intr",
		.reg = HGC_ITCT_ECC_ADDR,
	},
	{
		.irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF),
		.msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
		.shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
		.msg = "hgc_iostl_ecc1b_intr",
		.reg = HGC_LM_DFX_STATUS2,
	},
	{
		.irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF),
		.msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
		.shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
		.msg = "hgc_itctl_ecc1b_intr",
		.reg = HGC_LM_DFX_STATUS2,
	},
	{
		.irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_1B_OFF),
		.msk = HGC_CQE_ECC_1B_ADDR_MSK,
		.shift = HGC_CQE_ECC_1B_ADDR_OFF,
		.msg = "hgc_cqe_ecc1b_intr",
		.reg = HGC_CQE_ECC_ADDR,
	},
	{
		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF),
		.msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
		.shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
		.msg = "rxm_mem0_ecc1b_intr",
		.reg = HGC_RXM_DFX_STATUS14,
	},
	{
		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF),
		.msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
		.shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
		.msg = "rxm_mem1_ecc1b_intr",
		.reg = HGC_RXM_DFX_STATUS14,
	},

Annotation

• Immediate include surface: `hisi_sas.h`.
• Detected declarations: `struct hisi_sas_complete_v2_hdr`, `struct hisi_sas_err_record_v2`, `struct signal_attenuation_s`, `struct sig_atten_lu_s`, `function hisi_sas_read32`, `function hisi_sas_read32_relaxed`, `function hisi_sas_write32`, `function hisi_sas_phy_write32`, `function hisi_sas_phy_read32`, `function slot_index_alloc_quirk_v2_hw`.
• Atlas domain: Driver Families / drivers/scsi.
• Implementation status: source implementation candidate.
• Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.