drivers/scsi/mpt3sas/mpi/mpi2_ioc.h
Source file repositories/reference/linux-study-clean/drivers/scsi/mpt3sas/mpi/mpi2_ioc.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/scsi/mpt3sas/mpi/mpi2_ioc.h- Extension
.h- Size
- 77013 bytes
- Lines
- 1857
- Domain
- Driver Families
- Bucket
- drivers/scsi
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef MPI2_IOC_H
#define MPI2_IOC_H
/*****************************************************************************
*
* IOC Messages
*
*****************************************************************************/
/****************************************************************************
* IOCInit message
****************************************************************************/
/*IOCInit Request message */
typedef struct _MPI2_IOC_INIT_REQUEST {
U8 WhoInit; /*0x00 */
U8 Reserved1; /*0x01 */
U8 ChainOffset; /*0x02 */
U8 Function; /*0x03 */
U16 Reserved2; /*0x04 */
U8 Reserved3; /*0x06 */
U8 MsgFlags; /*0x07 */
U8 VP_ID; /*0x08 */
U8 VF_ID; /*0x09 */
U16 Reserved4; /*0x0A */
U16 MsgVersion; /*0x0C */
U16 HeaderVersion; /*0x0E */
U32 Reserved5; /*0x10 */
U16 ConfigurationFlags; /* 0x14 */
U8 HostPageSize; /*0x16 */
U8 HostMSIxVectors; /*0x17 */
U16 Reserved8; /*0x18 */
U16 SystemRequestFrameSize; /*0x1A */
U16 ReplyDescriptorPostQueueDepth; /*0x1C */
U16 ReplyFreeQueueDepth; /*0x1E */
U32 SenseBufferAddressHigh; /*0x20 */
U32 SystemReplyAddressHigh; /*0x24 */
U64 SystemRequestFrameBaseAddress; /*0x28 */
U64 ReplyDescriptorPostQueueAddress; /*0x30 */
U64 ReplyFreeQueueAddress; /*0x38 */
U64 TimeStamp; /*0x40 */
} MPI2_IOC_INIT_REQUEST, *PTR_MPI2_IOC_INIT_REQUEST,
Mpi2IOCInitRequest_t, *pMpi2IOCInitRequest_t;
/*WhoInit values */
#define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
#define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
#define MPI2_WHOINIT_ROM_BIOS (0x02)
#define MPI2_WHOINIT_PCI_PEER (0x03)
#define MPI2_WHOINIT_HOST_DRIVER (0x04)
#define MPI2_WHOINIT_MANUFACTURER (0x05)
/* MsgFlags */
#define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)
/*MsgVersion */
#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
/*HeaderVersion */
#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
#define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
/*ConfigurationFlags */
#define MPI26_IOCINIT_CFGFLAGS_NVME_SGL_FORMAT (0x0001)
#define MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE (0x0002)
/*minimum depth for a Reply Descriptor Post Queue */
#define MPI2_RDPQ_DEPTH_MIN (16)
/* Reply Descriptor Post Queue Array Entry */
typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
U64 RDPQBaseAddress; /* 0x00 */
U32 Reserved1; /* 0x08 */
U32 Reserved2; /* 0x0C */
} MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
*PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
Mpi2IOCInitRDPQArrayEntry, *pMpi2IOCInitRDPQArrayEntry;
/*IOCInit Reply message */
typedef struct _MPI2_IOC_INIT_REPLY {
U8 WhoInit; /*0x00 */
U8 Reserved1; /*0x01 */
U8 MsgLength; /*0x02 */
Annotation
- Atlas domain: Driver Families / drivers/scsi.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.