drivers/scsi/mpt3sas/mpi/mpi2_pci.h

File Facts

System

Linux kernel

Corpus path

drivers/scsi/mpt3sas/mpi/mpi2_pci.h

Extension

.h

Size

4612 bytes

Lines

114

Domain

Driver Families

Bucket

drivers/scsi

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef MPI2_PCI_H
#define MPI2_PCI_H


/*
 *Values for the PCIe DeviceInfo field used in PCIe Device Status Change Event
 *data and PCIe Configuration pages.
 */
#define MPI26_PCIE_DEVINFO_DIRECT_ATTACH        (0x00000010)

#define MPI26_PCIE_DEVINFO_MASK_DEVICE_TYPE     (0x0000000F)
#define MPI26_PCIE_DEVINFO_NO_DEVICE            (0x00000000)
#define MPI26_PCIE_DEVINFO_PCI_SWITCH           (0x00000001)
#define MPI26_PCIE_DEVINFO_NVME                 (0x00000003)
#define MPI26_PCIE_DEVINFO_SCSI                 (0x00000004)

/****************************************************************************
*  NVMe Encapsulated message
****************************************************************************/

/*NVME Encapsulated Request Message */
typedef struct _MPI26_NVME_ENCAPSULATED_REQUEST {
	U16	DevHandle;                      /*0x00 */
	U8	ChainOffset;                    /*0x02 */
	U8	Function;                       /*0x03 */
	U16	EncapsulatedCommandLength;      /*0x04 */
	U8	Reserved1;                      /*0x06 */
	U8	MsgFlags;                       /*0x07 */
	U8	VP_ID;                          /*0x08 */
	U8	VF_ID;                          /*0x09 */
	U16	Reserved2;                      /*0x0A */
	U32	Reserved3;                      /*0x0C */
	U64	ErrorResponseBaseAddress;       /*0x10 */
	U16	ErrorResponseAllocationLength;  /*0x18 */
	U16	Flags;                          /*0x1A */
	U32	DataLength;                     /*0x1C */
	U8	NVMe_Command[4];                /*0x20 */

} MPI26_NVME_ENCAPSULATED_REQUEST, *PTR_MPI26_NVME_ENCAPSULATED_REQUEST,
	Mpi26NVMeEncapsulatedRequest_t, *pMpi26NVMeEncapsulatedRequest_t;

/*defines for the Flags field */
#define MPI26_NVME_FLAGS_FORCE_ADMIN_ERR_RESP       (0x0020)
/*Submission Queue Type*/
#define MPI26_NVME_FLAGS_SUBMISSIONQ_MASK           (0x0010)
#define MPI26_NVME_FLAGS_SUBMISSIONQ_IO             (0x0000)
#define MPI26_NVME_FLAGS_SUBMISSIONQ_ADMIN          (0x0010)
/*Error Response Address Space */
#define MPI26_NVME_FLAGS_ERR_RSP_ADDR_MASK          (0x000C)
#define MPI26_NVME_FLAGS_ERR_RSP_ADDR_SYSTEM        (0x0000)
#define MPI26_NVME_FLAGS_ERR_RSP_ADDR_IOCTL         (0x0008)
/* Data Direction*/
#define MPI26_NVME_FLAGS_DATADIRECTION_MASK         (0x0003)
#define MPI26_NVME_FLAGS_NODATATRANSFER             (0x0000)
#define MPI26_NVME_FLAGS_WRITE                      (0x0001)
#define MPI26_NVME_FLAGS_READ                       (0x0002)
#define MPI26_NVME_FLAGS_BIDIRECTIONAL              (0x0003)


/*NVMe Encapuslated Reply Message */
typedef struct _MPI26_NVME_ENCAPSULATED_ERROR_REPLY {
	U16	DevHandle;                      /*0x00 */
	U8	MsgLength;                      /*0x02 */
	U8	Function;                       /*0x03 */
	U16	EncapsulatedCommandLength;      /*0x04 */
	U8	Reserved1;                      /*0x06 */
	U8	MsgFlags;                       /*0x07 */
	U8	VP_ID;                          /*0x08 */
	U8	VF_ID;                          /*0x09 */
	U16	Reserved2;                      /*0x0A */
	U16	Reserved3;                      /*0x0C */
	U16	IOCStatus;                      /*0x0E */
	U32	IOCLogInfo;                     /*0x10 */
	U16	ErrorResponseCount;             /*0x14 */
	U16	Reserved4;                      /*0x16 */
} MPI26_NVME_ENCAPSULATED_ERROR_REPLY,
	*PTR_MPI26_NVME_ENCAPSULATED_ERROR_REPLY,
	Mpi26NVMeEncapsulatedErrorReply_t,
	*pMpi26NVMeEncapsulatedErrorReply_t;


#endif

Annotation

• Atlas domain: Driver Families / drivers/scsi.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.