drivers/scsi/mvsas/mv_94xx.h

Source file repositories/reference/linux-study-clean/drivers/scsi/mvsas/mv_94xx.h

File Facts

System
Linux kernel
Corpus path
drivers/scsi/mvsas/mv_94xx.h
Extension
.h
Size
10232 bytes
Lines
334
Domain
Driver Families
Bucket
drivers/scsi
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct mvs_prd_imt {
#ifndef __BIG_ENDIAN
	__le32			len:22;
	u8			_r_a:2;
	u8			misc_ctl:4;
	u8			inter_sel:4;
#else
	u32			inter_sel:4;
	u32			misc_ctl:4;
	u32			_r_a:2;
	u32			len:22;
#endif
};

struct mvs_prd {
	/* 64-bit buffer address */
	__le64			addr;
	/* 22-bit length */
	__le32			im_len;
} __attribute__ ((packed));

enum sgpio_registers {
	MVS_SGPIO_HOST_OFFSET	= 0x100,	/* offset between hosts */

	MVS_SGPIO_CFG0	= 0xc200,
	MVS_SGPIO_CFG0_ENABLE	= (1 << 0),	/* enable pins */
	MVS_SGPIO_CFG0_BLINKB	= (1 << 1),	/* blink generators */
	MVS_SGPIO_CFG0_BLINKA	= (1 << 2),
	MVS_SGPIO_CFG0_INVSCLK	= (1 << 3),	/* invert signal? */
	MVS_SGPIO_CFG0_INVSLOAD	= (1 << 4),
	MVS_SGPIO_CFG0_INVSDOUT	= (1 << 5),
	MVS_SGPIO_CFG0_SLOAD_FALLEDGE = (1 << 6),	/* rise/fall edge? */
	MVS_SGPIO_CFG0_SDOUT_FALLEDGE = (1 << 7),
	MVS_SGPIO_CFG0_SDIN_RISEEDGE = (1 << 8),
	MVS_SGPIO_CFG0_MAN_BITLEN_SHIFT = 18,	/* bits/frame manual mode */
	MVS_SGPIO_CFG0_AUT_BITLEN_SHIFT = 24,	/* bits/frame auto mode */

	MVS_SGPIO_CFG1	= 0xc204,	/* blink timing register */
	MVS_SGPIO_CFG1_LOWA_SHIFT	= 0,	/* A off time */
	MVS_SGPIO_CFG1_HIA_SHIFT	= 4,	/* A on time */
	MVS_SGPIO_CFG1_LOWB_SHIFT	= 8,	/* B off time */
	MVS_SGPIO_CFG1_HIB_SHIFT	= 12,	/* B on time */
	MVS_SGPIO_CFG1_MAXACTON_SHIFT	= 16,	/* max activity on time */

		/* force activity off time */
	MVS_SGPIO_CFG1_FORCEACTOFF_SHIFT	= 20,
		/* stretch activity on time */
	MVS_SGPIO_CFG1_STRCHACTON_SHIFT	= 24,
		/* stretch activiity off time */
	MVS_SGPIO_CFG1_STRCHACTOFF_SHIFT	= 28,


	MVS_SGPIO_CFG2	= 0xc208,	/* clock speed register */
	MVS_SGPIO_CFG2_CLK_SHIFT	= 0,
	MVS_SGPIO_CFG2_BLINK_SHIFT	= 20,

	MVS_SGPIO_CTRL	= 0xc20c,	/* SDOUT/SDIN mode control */
	MVS_SGPIO_CTRL_SDOUT_AUTO	= 2,
	MVS_SGPIO_CTRL_SDOUT_SHIFT	= 2,

	MVS_SGPIO_DSRC	= 0xc220,	/* map ODn bits to drives */

	MVS_SGPIO_DCTRL	= 0xc238,
	MVS_SGPIO_DCTRL_ERR_SHIFT	= 0,
	MVS_SGPIO_DCTRL_LOC_SHIFT	= 3,
	MVS_SGPIO_DCTRL_ACT_SHIFT	= 5,
};

enum sgpio_led_status {
	LED_OFF	= 0,
	LED_ON	= 1,
	LED_BLINKA	= 2,
	LED_BLINKA_INV	= 3,
	LED_BLINKA_SOF	= 4,
	LED_BLINKA_EOF	= 5,
	LED_BLINKB	= 6,
	LED_BLINKB_INV	= 7,
};

#define DEFAULT_SGPIO_BITS ((LED_BLINKA_SOF << \
				MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 3) | \
			(LED_BLINKA_SOF << \
				MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 2) | \
			(LED_BLINKA_SOF << \
				MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 1) | \
			(LED_BLINKA_SOF << \
				MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 0))

/*
 * these registers are accessed through port vendor

Annotation

Implementation Notes