drivers/scsi/qla1280.h
Source file repositories/reference/linux-study-clean/drivers/scsi/qla1280.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/scsi/qla1280.h- Extension
.h- Size
- 35145 bytes
- Lines
- 1072
- Domain
- Driver Families
- Bucket
- drivers/scsi
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct srbstruct device_regstruct nvramstruct cmd_entrystruct cont_entrystruct responsestruct mrk_entrystruct ecmd_entrystruct cont_a64_entrystruct elun_entrystruct modify_lun_entrystruct notify_entrystruct nack_entrystruct atio_entrystruct ctio_entrystruct ctio_ret_entrystruct ctio_a64_entrystruct ctio_a64_ret_entrystruct bus_paramstruct qla_driver_setupstruct scsi_qla_host
Annotated Snippet
struct srb {
struct list_head list; /* (8/16) LU queue */
struct scsi_cmnd *cmd; /* (4/8) SCSI command block */
/* NOTE: the sp->cmd will be NULL when this completion is
* called, so you should know the scsi_cmnd when using this */
struct completion *wait;
dma_addr_t saved_dma_handle; /* for unmap of single transfers */
uint8_t flags; /* (1) Status flags. */
uint8_t dir; /* direction of transfer */
};
/*
* SRB flag definitions
*/
#define SRB_TIMEOUT (1 << 0) /* Command timed out */
#define SRB_SENT (1 << 1) /* Command sent to ISP */
#define SRB_ABORT_PENDING (1 << 2) /* Command abort sent to device */
#define SRB_ABORTED (1 << 3) /* Command aborted command already */
/*
* ISP I/O Register Set structure definitions.
*/
struct device_reg {
uint16_t id_l; /* ID low */
uint16_t id_h; /* ID high */
uint16_t cfg_0; /* Configuration 0 */
#define ISP_CFG0_HWMSK 0x000f /* Hardware revision mask */
#define ISP_CFG0_1020 1 /* ISP1020 */
#define ISP_CFG0_1020A 2 /* ISP1020A */
#define ISP_CFG0_1040 3 /* ISP1040 */
#define ISP_CFG0_1040A 4 /* ISP1040A */
#define ISP_CFG0_1040B 5 /* ISP1040B */
#define ISP_CFG0_1040C 6 /* ISP1040C */
uint16_t cfg_1; /* Configuration 1 */
#define ISP_CFG1_F128 BIT_6 /* 128-byte FIFO threshold */
#define ISP_CFG1_F64 BIT_4|BIT_5 /* 128-byte FIFO threshold */
#define ISP_CFG1_F32 BIT_5 /* 128-byte FIFO threshold */
#define ISP_CFG1_F16 BIT_4 /* 128-byte FIFO threshold */
#define ISP_CFG1_BENAB BIT_2 /* Global Bus burst enable */
#define ISP_CFG1_SXP BIT_0 /* SXP register select */
uint16_t ictrl; /* Interface control */
#define ISP_RESET BIT_0 /* ISP soft reset */
#define ISP_EN_INT BIT_1 /* ISP enable interrupts. */
#define ISP_EN_RISC BIT_2 /* ISP enable RISC interrupts. */
#define ISP_FLASH_ENABLE BIT_8 /* Flash BIOS Read/Write enable */
#define ISP_FLASH_UPPER BIT_9 /* Flash upper bank select */
uint16_t istatus; /* Interface status */
#define PCI_64BIT_SLOT BIT_14 /* PCI 64-bit slot indicator. */
#define RISC_INT BIT_2 /* RISC interrupt */
#define PCI_INT BIT_1 /* PCI interrupt */
uint16_t semaphore; /* Semaphore */
uint16_t nvram; /* NVRAM register. */
#define NV_DESELECT 0
#define NV_CLOCK BIT_0
#define NV_SELECT BIT_1
#define NV_DATA_OUT BIT_2
#define NV_DATA_IN BIT_3
uint16_t flash_data; /* Flash BIOS data */
uint16_t flash_address; /* Flash BIOS address */
uint16_t unused_1[0x06];
/* cdma_* and ddma_* are 1040 only */
uint16_t cdma_cfg;
#define CDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */
#define CDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */
#define CDMA_CONF_BENAB BIT_1 /* Bus burst enable */
#define CDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */
uint16_t cdma_ctrl;
uint16_t cdma_status;
uint16_t cdma_fifo_status;
uint16_t cdma_count;
uint16_t cdma_reserved;
uint16_t cdma_address_count_0;
uint16_t cdma_address_count_1;
uint16_t cdma_address_count_2;
uint16_t cdma_address_count_3;
uint16_t unused_2[0x06];
uint16_t ddma_cfg;
#define DDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */
#define DDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */
#define DDMA_CONF_BENAB BIT_1 /* Bus burst enable */
#define DDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */
uint16_t ddma_ctrl;
uint16_t ddma_status;
uint16_t ddma_fifo_status;
uint16_t ddma_xfer_count_low;
uint16_t ddma_xfer_count_high;
Annotation
- Detected declarations: `struct srb`, `struct device_reg`, `struct nvram`, `struct cmd_entry`, `struct cont_entry`, `struct response`, `struct mrk_entry`, `struct ecmd_entry`, `struct cont_a64_entry`, `struct elun_entry`.
- Atlas domain: Driver Families / drivers/scsi.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.