drivers/scsi/qla2xxx/qla_bsg.h
Source file repositories/reference/linux-study-clean/drivers/scsi/qla2xxx/qla_bsg.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/scsi/qla2xxx/qla_bsg.h- Extension
.h- Size
- 9320 bytes
- Lines
- 336
- Domain
- Driver Families
- Bucket
- drivers/scsi
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
qla_edif_bsg.h
Detected Declarations
struct qla84_mgmt_paramstruct qla84_msg_mgmtstruct qla_bsg_a84_mgmtstruct qla_scsi_addrstruct qla_ext_dest_addrstruct qla_port_paramstruct qla_mbx_passthrustruct qla_field_addressstruct qla_field_infostruct qla_image_versionstruct qla_image_version_liststruct qla_status_regstruct qla_i2c_accessstruct qla_serdes_regstruct qla_serdes_reg_exstruct qla_flash_update_capsstruct qla_bbcr_datastruct qla_dport_diagstruct qla_dport_diag_v2struct qla_active_regionsstruct qla_drv_attr
Annotated Snippet
struct qla84_mgmt_param {
union {
struct {
uint32_t start_addr;
} mem; /* for QLA84_MGMT_READ/WRITE_MEM */
struct {
uint32_t id;
#define QLA84_MGMT_CONFIG_ID_UIF 1
#define QLA84_MGMT_CONFIG_ID_FCOE_COS 2
#define QLA84_MGMT_CONFIG_ID_PAUSE 3
#define QLA84_MGMT_CONFIG_ID_TIMEOUTS 4
uint32_t param0;
uint32_t param1;
} config; /* for QLA84_MGMT_CHNG_CONFIG */
struct {
uint32_t type;
#define QLA84_MGMT_INFO_CONFIG_LOG_DATA 1 /* Get Config Log Data */
#define QLA84_MGMT_INFO_LOG_DATA 2 /* Get Log Data */
#define QLA84_MGMT_INFO_PORT_STAT 3 /* Get Port Statistics */
#define QLA84_MGMT_INFO_LIF_STAT 4 /* Get LIF Statistics */
#define QLA84_MGMT_INFO_ASIC_STAT 5 /* Get ASIC Statistics */
#define QLA84_MGMT_INFO_CONFIG_PARAMS 6 /* Get Config Parameters */
#define QLA84_MGMT_INFO_PANIC_LOG 7 /* Get Panic Log */
uint32_t context;
/*
* context definitions for QLA84_MGMT_INFO_CONFIG_LOG_DATA
*/
#define IC_LOG_DATA_LOG_ID_DEBUG_LOG 0
#define IC_LOG_DATA_LOG_ID_LEARN_LOG 1
#define IC_LOG_DATA_LOG_ID_FC_ACL_INGRESS_LOG 2
#define IC_LOG_DATA_LOG_ID_FC_ACL_EGRESS_LOG 3
#define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_INGRESS_LOG 4
#define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_EGRESS_LOG 5
#define IC_LOG_DATA_LOG_ID_MESSAGE_TRANSMIT_LOG 6
#define IC_LOG_DATA_LOG_ID_MESSAGE_RECEIVE_LOG 7
#define IC_LOG_DATA_LOG_ID_LINK_EVENT_LOG 8
#define IC_LOG_DATA_LOG_ID_DCX_LOG 9
/*
* context definitions for QLA84_MGMT_INFO_PORT_STAT
*/
#define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT0 0
#define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT1 1
#define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT0 2
#define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT1 3
#define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT0 4
#define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT1 5
/*
* context definitions for QLA84_MGMT_INFO_LIF_STAT
*/
#define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT0 0
#define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT1 1
#define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT0 2
#define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT1 3
#define IC_LIF_STATISTICS_LIF_NUMBER_CPU 6
} info; /* for QLA84_MGMT_GET_INFO */
} u;
};
struct qla84_msg_mgmt {
uint16_t cmd;
#define QLA84_MGMT_READ_MEM 0x00
#define QLA84_MGMT_WRITE_MEM 0x01
#define QLA84_MGMT_CHNG_CONFIG 0x02
#define QLA84_MGMT_GET_INFO 0x03
uint16_t rsrvd;
struct qla84_mgmt_param mgmtp;/* parameters for cmd */
uint32_t len; /* bytes in payload following this struct */
uint8_t payload[]; /* payload for cmd */
};
struct qla_bsg_a84_mgmt {
struct qla84_msg_mgmt mgmt;
} __attribute__ ((packed));
struct qla_scsi_addr {
uint16_t bus;
uint16_t target;
} __attribute__ ((packed));
struct qla_ext_dest_addr {
union {
uint8_t wwnn[8];
uint8_t wwpn[8];
Annotation
- Immediate include surface: `qla_edif_bsg.h`.
- Detected declarations: `struct qla84_mgmt_param`, `struct qla84_msg_mgmt`, `struct qla_bsg_a84_mgmt`, `struct qla_scsi_addr`, `struct qla_ext_dest_addr`, `struct qla_port_param`, `struct qla_mbx_passthru`, `struct qla_field_address`, `struct qla_field_info`, `struct qla_image_version`.
- Atlas domain: Driver Families / drivers/scsi.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.