drivers/scsi/qla2xxx/qla_nx.c
Source file repositories/reference/linux-study-clean/drivers/scsi/qla2xxx/qla_nx.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/scsi/qla2xxx/qla_nx.c- Extension
.c- Size
- 116499 bytes
- Lines
- 4428
- Domain
- Driver Families
- Bucket
- drivers/scsi
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
qla_def.hlinux/delay.hlinux/io-64-nonatomic-lo-hi.hlinux/pci.hlinux/ratelimit.hlinux/vmalloc.hscsi/scsi_tcq.h
Detected Declarations
function qla82xx_crb_addr_transform_setupfunction qla82xx_pci_set_crbwindow_2Mfunction qla82xx_pci_get_crb_addr_2Mfunction qla82xx_crb_win_lockfunction qla82xx_wr_32function qla82xx_rd_32function qla82xx_idc_lockfunction qla82xx_idc_unlockfunction qla82xx_pci_mem_bound_checkfunction qla82xx_pci_set_windowfunction qla82xx_pci_is_same_windowfunction qla82xx_pci_mem_read_directfunction qla82xx_pci_mem_write_directfunction qla82xx_decode_crb_addrfunction qla82xx_rom_lockfunction qla82xx_rom_unlockfunction qla82xx_wait_rom_busyfunction qla82xx_wait_rom_donefunction qla82xx_md_rw_32function qla82xx_do_rom_fast_readfunction qla82xx_rom_fast_readfunction qla82xx_read_status_regfunction qla82xx_flash_wait_write_finishfunction qla82xx_flash_set_write_enablefunction qla82xx_write_status_regfunction qla82xx_write_disable_flashfunction ql82xx_rom_lock_dfunction qla82xx_write_flash_dwordfunction qla82xx_pinit_from_romfunction qla82xx_rom_fast_readfunction qla82xx_pci_mem_write_2Mfunction qla82xx_fw_load_from_flashfunction qla82xx_pci_mem_read_2Mfunction qla82xx_get_table_descfunction qla82xx_get_data_descfunction qla82xx_get_bootld_offsetfunction qla82xx_get_fw_sizefunction qla82xx_get_fw_offsfunction qla82xx_iospace_configfunction qla82xx_pci_configfunction qla82xx_reset_chipfunction qla82xx_config_ringsfunction qla82xx_fw_load_from_blobfunction qla82xx_set_product_offsetfunction qla82xx_validate_firmware_blobfunction qla82xx_check_cmdpeg_statefunction qla82xx_check_rcvpeg_statefunction qla82xx_mbx_completion
Annotated Snippet
if ((win_read << 17) != window) {
ql_dbg(ql_dbg_p3p, vha, 0xb003,
"%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
__func__, window, win_read);
}
addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
} else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
QLA82XX_ADDR_OCM0_MAX)) {
unsigned int temp1;
if ((addr & 0x00ff800) == 0xff800) {
ql_log(ql_log_warn, vha, 0xb004,
"%s: QM access not handled.\n", __func__);
addr = -1UL;
}
window = OCM_WIN(addr);
ha->ddr_mn_window = window;
qla82xx_wr_32(ha,
ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
win_read = qla82xx_rd_32(ha,
ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
temp1 = ((window & 0x1FF) << 7) |
((window & 0x0FFFE0000) >> 17);
if (win_read != temp1) {
ql_log(ql_log_warn, vha, 0xb005,
"%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
__func__, temp1, win_read);
}
addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
} else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET,
QLA82XX_P3_ADDR_QDR_NET_MAX)) {
/* QDR network side */
window = MS_WIN(addr);
ha->qdr_sn_window = window;
qla82xx_wr_32(ha,
ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
win_read = qla82xx_rd_32(ha,
ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
if (win_read != window) {
ql_log(ql_log_warn, vha, 0xb006,
"%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
__func__, window, win_read);
}
addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
} else {
/*
* peg gdb frequently accesses memory that doesn't exist,
* this limits the chit chat so debugging isn't slowed down.
*/
if ((qla82xx_pci_set_window_warning_count++ < 8) ||
(qla82xx_pci_set_window_warning_count%64 == 0)) {
ql_log(ql_log_warn, vha, 0xb007,
"%s: Warning:%s Unknown address range!.\n",
__func__, QLA2XXX_DRIVER_NAME);
}
addr = -1UL;
}
return addr;
}
/* check if address is in the same windows as the previous access */
static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
unsigned long long addr)
{
int window;
unsigned long long qdr_max;
qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
/* DDR network side */
if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
QLA82XX_ADDR_DDR_NET_MAX))
BUG();
else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
QLA82XX_ADDR_OCM0_MAX))
return 1;
else if (addr_in_range(addr, QLA82XX_ADDR_OCM1,
QLA82XX_ADDR_OCM1_MAX))
return 1;
else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
/* QDR network side */
window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
if (ha->qdr_sn_window == window)
return 1;
}
return 0;
}
static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
Annotation
- Immediate include surface: `qla_def.h`, `linux/delay.h`, `linux/io-64-nonatomic-lo-hi.h`, `linux/pci.h`, `linux/ratelimit.h`, `linux/vmalloc.h`, `scsi/scsi_tcq.h`.
- Detected declarations: `function qla82xx_crb_addr_transform_setup`, `function qla82xx_pci_set_crbwindow_2M`, `function qla82xx_pci_get_crb_addr_2M`, `function qla82xx_crb_win_lock`, `function qla82xx_wr_32`, `function qla82xx_rd_32`, `function qla82xx_idc_lock`, `function qla82xx_idc_unlock`, `function qla82xx_pci_mem_bound_check`, `function qla82xx_pci_set_window`.
- Atlas domain: Driver Families / drivers/scsi.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.