drivers/scsi/qla4xxx/ql4_fw.h

Source file repositories/reference/linux-study-clean/drivers/scsi/qla4xxx/ql4_fw.h

File Facts

System
Linux kernel
Corpus path
drivers/scsi/qla4xxx/ql4_fw.h
Extension
.h
Size
45781 bytes
Lines
1442
Domain
Driver Families
Bucket
drivers/scsi
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct port_ctrl_stat_regs {
	__le32 ext_hw_conf;	/* 0x50  R/W */
	__le32 rsrvd0;		/* 0x54 */
	__le32 port_ctrl;	/* 0x58 */
	__le32 port_status;	/* 0x5c */
	__le32 rsrvd1[32];	/* 0x60-0xdf */
	__le32 gp_out;		/* 0xe0 */
	__le32 gp_in;		/* 0xe4 */
	__le32 rsrvd2[5];	/* 0xe8-0xfb */
	__le32 port_err_status; /* 0xfc */
};

struct host_mem_cfg_regs {
	__le32 rsrvd0[12];	/* 0x50-0x79 */
	__le32 req_q_out;	/* 0x80 */
	__le32 rsrvd1[31];	/* 0x84-0xFF */
};

/*
 * ISP 82xx I/O Register Set structure definitions.
 */
struct device_reg_82xx {
	__le32 req_q_out;	/* 0x0000 (R): Request Queue out-Pointer. */
	__le32 reserve1[63];	/* Request Queue out-Pointer. (64 * 4) */
	__le32 rsp_q_in;	/* 0x0100 (R/W): Response Queue In-Pointer. */
	__le32 reserve2[63];	/* Response Queue In-Pointer. */
	__le32 rsp_q_out;	/* 0x0200 (R/W): Response Queue Out-Pointer. */
	__le32 reserve3[63];	/* Response Queue Out-Pointer. */

	__le32 mailbox_in[8];	/* 0x0300 (R/W): Mail box In registers */
	__le32 reserve4[24];
	__le32 hint;		/* 0x0380 (R/W): Host interrupt register */
#define HINT_MBX_INT_PENDING	BIT_0
	__le32 reserve5[31];
	__le32 mailbox_out[8];	/* 0x0400 (R): Mail box Out registers */
	__le32 reserve6[56];

	__le32 host_status;	/* Offset 0x500 (R): host status */
#define HSRX_RISC_MB_INT	BIT_0  /* RISC to Host Mailbox interrupt */
#define HSRX_RISC_IOCB_INT	BIT_1  /* RISC to Host IOCB interrupt */

	__le32 host_int;	/* Offset 0x0504 (R/W): Interrupt status. */
#define ISRX_82XX_RISC_INT	BIT_0 /* RISC interrupt. */
};

/* ISP 83xx I/O Register Set structure */
struct device_reg_83xx {
	__le32 mailbox_in[16];	/* 0x0000 */
	__le32 reserve1[496];	/* 0x0040 */
	__le32 mailbox_out[16];	/* 0x0800 */
	__le32 reserve2[496];
	__le32 mbox_int;	/* 0x1000 */
	__le32 reserve3[63];
	__le32 req_q_out;	/* 0x1100 */
	__le32 reserve4[63];

	__le32 rsp_q_in;	/* 0x1200 */
	__le32 reserve5[1919];

	__le32 req_q_in;	/* 0x3000 */
	__le32 reserve6[3];
	__le32 iocb_int_mask;	/* 0x3010 */
	__le32 reserve7[3];
	__le32 rsp_q_out;	/* 0x3020 */
	__le32 reserve8[3];
	__le32 anonymousbuff;	/* 0x3030 */
	__le32 mb_int_mask;	/* 0x3034 */

	__le32 host_intr;	/* 0x3038 - Host Interrupt Register */
	__le32 risc_intr;	/* 0x303C - RISC Interrupt Register */
	__le32 reserve9[544];
	__le32 leg_int_ptr;	/* 0x38C0 - Legacy Interrupt Pointer Register */
	__le32 leg_int_trig;	/* 0x38C4 - Legacy Interrupt Trigger Control */
	__le32 leg_int_mask;	/* 0x38C8 - Legacy Interrupt Mask Register */
};

#define INT_ENABLE_FW_MB	(1 << 2)
#define INT_MASK_FW_MB		(1 << 2)

/*  remote register set (access via PCI memory read/write) */
struct isp_reg {
#define MBOX_REG_COUNT 8
	__le32 mailbox[MBOX_REG_COUNT];

	__le32 flash_address;	/* 0x20 */
	__le32 flash_data;
	__le32 ctrl_status;

	union {
		struct {

Annotation

Implementation Notes