drivers/scsi/qla4xxx/ql4_nx.c
Source file repositories/reference/linux-study-clean/drivers/scsi/qla4xxx/ql4_nx.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/scsi/qla4xxx/ql4_nx.c- Extension
.c- Size
- 117177 bytes
- Lines
- 4205
- Domain
- Driver Families
- Bucket
- drivers/scsi
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/delay.hlinux/io.hlinux/pci.hlinux/ratelimit.hql4_def.hql4_glbl.hql4_inline.hlinux/io-64-nonatomic-lo-hi.h
Detected Declarations
function Copyrightfunction qla4_82xx_crb_addr_transform_setupfunction qla4_82xx_pci_set_crbwindow_2Mfunction qla4_82xx_crb_win_lockfunction qla4_82xx_crb_win_unlockfunction qla4_82xx_wr_32function qla4_82xx_rd_32function qla4_82xx_md_rd_32function qla4_82xx_md_wr_32function qla4_82xx_idc_lockfunction qla4_82xx_idc_unlockfunction qla4_82xx_pci_get_crb_addr_2Mfunction qla4_82xx_pci_mem_bound_checkfunction qla4_82xx_pci_set_windowfunction qla4_82xx_pci_is_same_windowfunction qla4_82xx_pci_mem_read_directfunction qla4_82xx_pci_mem_write_directfunction qla4_82xx_decode_crb_addrfunction qla4_82xx_rom_lockfunction qla4_82xx_rom_unlockfunction qla4_82xx_wait_rom_donefunction qla4_82xx_do_rom_fast_readfunction qla4_82xx_rom_fast_readfunction qla4_82xx_pinit_from_romfunction qla4_82xx_rom_fast_readfunction qla4_8xxx_ms_mem_write_128bfunction qla4_82xx_load_from_flashfunction qla4_82xx_load_fwfunction qla4_82xx_pci_mem_read_2Mfunction qla4_82xx_pci_mem_write_2Mfunction qla4_82xx_cmdpeg_readyfunction qla4_82xx_rcvpeg_readyfunction qla4_8xxx_set_drv_activefunction qla4_8xxx_clear_drv_activefunction qla4_8xxx_need_resetfunction qla4_8xxx_set_rst_readyfunction qla4_8xxx_clear_rst_readyfunction qla4_8xxx_set_qsnt_readyfunction qla4_82xx_start_firmwarefunction qla4_82xx_try_start_fwfunction qla4_82xx_rom_lock_recoveryfunction ql4_84xx_poll_wait_for_readyfunction ql4_84xx_ipmdio_rd_regfunction ql4_84xx_poll_wait_ipmdio_bus_idlefunction ql4_84xx_ipmdio_wr_regfunction qla4_8xxx_minidump_process_rdcrbfunction qla4_83xx_check_dma_engine_statefunction qla4_83xx_start_pex_dma
Annotated Snippet
if ((win_read << 17) != window) {
ql4_printk(KERN_WARNING, ha,
"%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
__func__, window, win_read);
}
addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
} else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
QLA8XXX_ADDR_OCM0_MAX)) {
unsigned int temp1;
/* if bits 19:18&17:11 are on */
if ((addr & 0x00ff800) == 0xff800) {
printk("%s: QM access not handled.\n", __func__);
addr = -1UL;
}
window = OCM_WIN(addr);
ha->ddr_mn_window = window;
qla4_82xx_wr_32(ha, ha->mn_win_crb |
QLA82XX_PCI_CRBSPACE, window);
win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
QLA82XX_PCI_CRBSPACE);
temp1 = ((window & 0x1FF) << 7) |
((window & 0x0FFFE0000) >> 17);
if (win_read != temp1) {
printk("%s: Written OCMwin (0x%x) != Read"
" OCMwin (0x%x)\n", __func__, temp1, win_read);
}
addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
} else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
QLA82XX_P3_ADDR_QDR_NET_MAX)) {
/* QDR network side */
window = MS_WIN(addr);
ha->qdr_sn_window = window;
qla4_82xx_wr_32(ha, ha->ms_win_crb |
QLA82XX_PCI_CRBSPACE, window);
win_read = qla4_82xx_rd_32(ha,
ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
if (win_read != window) {
printk("%s: Written MSwin (0x%x) != Read "
"MSwin (0x%x)\n", __func__, window, win_read);
}
addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
} else {
/*
* peg gdb frequently accesses memory that doesn't exist,
* this limits the chit chat so debugging isn't slowed down.
*/
if ((qla4_82xx_pci_set_window_warning_count++ < 8) ||
(qla4_82xx_pci_set_window_warning_count%64 == 0)) {
printk("%s: Warning:%s Unknown address range!\n",
__func__, DRIVER_NAME);
}
addr = -1UL;
}
return addr;
}
/* check if address is in the same windows as the previous access */
static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha,
unsigned long long addr)
{
int window;
unsigned long long qdr_max;
qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_DDR_NET,
QLA8XXX_ADDR_DDR_NET_MAX)) {
/* DDR network side */
BUG(); /* MN access can not come here */
} else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM0,
QLA8XXX_ADDR_OCM0_MAX)) {
return 1;
} else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_OCM1,
QLA8XXX_ADDR_OCM1_MAX)) {
return 1;
} else if (QLA8XXX_ADDR_IN_RANGE(addr, QLA8XXX_ADDR_QDR_NET,
qdr_max)) {
/* QDR network side */
window = ((addr - QLA8XXX_ADDR_QDR_NET) >> 22) & 0x3f;
if (ha->qdr_sn_window == window)
return 1;
}
return 0;
}
static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha,
Annotation
- Immediate include surface: `linux/delay.h`, `linux/io.h`, `linux/pci.h`, `linux/ratelimit.h`, `ql4_def.h`, `ql4_glbl.h`, `ql4_inline.h`, `linux/io-64-nonatomic-lo-hi.h`.
- Detected declarations: `function Copyright`, `function qla4_82xx_crb_addr_transform_setup`, `function qla4_82xx_pci_set_crbwindow_2M`, `function qla4_82xx_crb_win_lock`, `function qla4_82xx_crb_win_unlock`, `function qla4_82xx_wr_32`, `function qla4_82xx_rd_32`, `function qla4_82xx_md_rd_32`, `function qla4_82xx_md_wr_32`, `function qla4_82xx_idc_lock`.
- Atlas domain: Driver Families / drivers/scsi.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.