drivers/scsi/smartpqi/smartpqi.h

Source file repositories/reference/linux-study-clean/drivers/scsi/smartpqi/smartpqi.h

File Facts

System
Linux kernel
Corpus path
drivers/scsi/smartpqi/smartpqi.h
Extension
.h
Size
47566 bytes
Lines
1719
Domain
Driver Families
Bucket
drivers/scsi
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct pqi_device_registers {
	__le64	signature;
	u8	function_and_status_code;
	u8	reserved[7];
	u8	max_admin_iq_elements;
	u8	max_admin_oq_elements;
	u8	admin_iq_element_length;	/* in 16-byte units */
	u8	admin_oq_element_length;	/* in 16-byte units */
	__le16	max_reset_timeout;		/* in 100-millisecond units */
	u8	reserved1[2];
	__le32	legacy_intx_status;
	__le32	legacy_intx_mask_set;
	__le32	legacy_intx_mask_clear;
	u8	reserved2[28];
	__le32	device_status;
	u8	reserved3[4];
	__le64	admin_iq_pi_offset;
	__le64	admin_oq_ci_offset;
	__le64	admin_iq_element_array_addr;
	__le64	admin_oq_element_array_addr;
	__le64	admin_iq_ci_addr;
	__le64	admin_oq_pi_addr;
	u8	admin_iq_num_elements;
	u8	admin_oq_num_elements;
	__le16	admin_queue_int_msg_num;
	u8	reserved4[4];
	__le32	device_error;
	u8	reserved5[4];
	__le64	error_details;
	__le32	device_reset;
	__le32	power_action;
	u8	reserved6[104];
};

/*
 * controller registers
 *
 * These are defined by the Microchip implementation.
 *
 * Some registers (those named sis_*) are only used when in
 * legacy SIS mode before we transition the controller into
 * PQI mode.  There are a number of other SIS mode registers,
 * but we don't use them, so only the SIS registers that we
 * care about are defined here.  The offsets mentioned in the
 * comments are the offsets from the PCIe BAR 0.
 */
struct pqi_ctrl_registers {
	u8	reserved[0x20];
	__le32	sis_host_to_ctrl_doorbell;		/* 20h */
	u8	reserved1[0x34 - (0x20 + sizeof(__le32))];
	__le32	sis_interrupt_mask;			/* 34h */
	u8	reserved2[0x9c - (0x34 + sizeof(__le32))];
	__le32	sis_ctrl_to_host_doorbell;		/* 9Ch */
	u8	reserved3[0xa0 - (0x9c + sizeof(__le32))];
	__le32	sis_ctrl_to_host_doorbell_clear;	/* A0h */
	u8	reserved4[0xb0 - (0xa0 + sizeof(__le32))];
	__le32	sis_driver_scratch;			/* B0h */
	__le32  sis_product_identifier;			/* B4h */
	u8	reserved5[0xbc - (0xb4 + sizeof(__le32))];
	__le32	sis_firmware_status;			/* BCh */
	u8	reserved6[0xcc - (0xbc + sizeof(__le32))];
	__le32	sis_ctrl_shutdown_reason_code;		/* CCh */
	u8	reserved7[0x1000 - (0xcc + sizeof(__le32))];
	__le32	sis_mailbox[8];				/* 1000h */
	u8	reserved8[0x4000 - (0x1000 + (sizeof(__le32) * 8))];
	/*
	 * The PQI spec states that the PQI registers should be at
	 * offset 0 from the PCIe BAR 0.  However, we can't map
	 * them at offset 0 because that would break compatibility
	 * with the SIS registers.  So we map them at offset 4000h.
	 */
	struct pqi_device_registers pqi_registers;	/* 4000h */
};

#define PQI_DEVICE_REGISTERS_OFFSET	0x4000

/* shutdown reasons for taking the controller offline */
enum pqi_ctrl_shutdown_reason {
	PQI_IQ_NOT_DRAINED_TIMEOUT = 1,
	PQI_LUN_RESET_TIMEOUT = 2,
	PQI_IO_PENDING_POST_LUN_RESET_TIMEOUT = 3,
	PQI_NO_HEARTBEAT = 4,
	PQI_FIRMWARE_KERNEL_NOT_UP = 5,
	PQI_OFA_RESPONSE_TIMEOUT = 6,
	PQI_INVALID_REQ_ID = 7,
	PQI_UNMATCHED_REQ_ID = 8,
	PQI_IO_PI_OUT_OF_RANGE = 9,
	PQI_EVENT_PI_OUT_OF_RANGE = 10,
	PQI_UNEXPECTED_IU_TYPE = 11
};

Annotation

Implementation Notes