drivers/soc/bcm/brcmstb/pm/pm-mips.c

Source file repositories/reference/linux-study-clean/drivers/soc/bcm/brcmstb/pm/pm-mips.c

File Facts

System
Linux kernel
Corpus path
drivers/soc/bcm/brcmstb/pm/pm-mips.c
Extension
.c
Size
10603 bytes
Lines
457
Domain
Driver Families
Bucket
drivers/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct brcmstb_memc {
	void __iomem *ddr_phy_base;
	void __iomem *arb_base;
};

struct brcmstb_pm_control {
	void __iomem *aon_ctrl_base;
	void __iomem *aon_sram_base;
	void __iomem *timers_base;
	struct brcmstb_memc memcs[MAX_NUM_MEMC];
	int num_memc;
};

struct brcm_pm_s3_context {
	u32			cp0_regs[MAX_CP0_REGS];
	u32			memc0_rts[NUM_MEMC_CLIENTS];
	u32			sc_boot_vec;
};

struct brcmstb_mem_transfer;

struct brcmstb_mem_transfer {
	struct brcmstb_mem_transfer	*next;
	void				*src;
	void				*dst;
	dma_addr_t			pa_src;
	dma_addr_t			pa_dst;
	u32				len;
	u8				key;
	u8				mode;
	u8				src_remapped;
	u8				dst_remapped;
	u8				src_dst_remapped;
};

#define AON_SAVE_SRAM(base, idx, val) \
	__raw_writel(val, base + (idx << 2))

/* Used for saving registers in asm */
u32 gp_regs[MAX_GP_REGS];

#define	BSP_CLOCK_STOP		0x00
#define PM_INITIATE		0x01

static struct brcmstb_pm_control ctrl;

static void brcm_pm_save_cp0_context(struct brcm_pm_s3_context *ctx)
{
	/* Generic MIPS */
	ctx->cp0_regs[CONTEXT] = read_c0_context();
	ctx->cp0_regs[USER_LOCAL] = read_c0_userlocal();
	ctx->cp0_regs[PGMK] = read_c0_pagemask();
	ctx->cp0_regs[HWRENA] = read_c0_cache();
	ctx->cp0_regs[COMPARE] = read_c0_compare();
	ctx->cp0_regs[STATUS] = read_c0_status();

	/* Broadcom specific */
	ctx->cp0_regs[CONFIG] = read_c0_brcm_config();
	ctx->cp0_regs[MODE] = read_c0_brcm_mode();
	ctx->cp0_regs[EDSP] = read_c0_brcm_edsp();
	ctx->cp0_regs[BOOT_VEC] = read_c0_brcm_bootvec();
	ctx->cp0_regs[EBASE] = read_c0_ebase();

	ctx->sc_boot_vec = bmips_read_zscm_reg(0xa0);
}

static void brcm_pm_restore_cp0_context(struct brcm_pm_s3_context *ctx)
{
	/* Restore cp0 state */
	bmips_write_zscm_reg(0xa0, ctx->sc_boot_vec);

	/* Generic MIPS */
	write_c0_context(ctx->cp0_regs[CONTEXT]);
	write_c0_userlocal(ctx->cp0_regs[USER_LOCAL]);
	write_c0_pagemask(ctx->cp0_regs[PGMK]);
	write_c0_cache(ctx->cp0_regs[HWRENA]);
	write_c0_compare(ctx->cp0_regs[COMPARE]);
	write_c0_status(ctx->cp0_regs[STATUS]);

	/* Broadcom specific */
	write_c0_brcm_config(ctx->cp0_regs[CONFIG]);
	write_c0_brcm_mode(ctx->cp0_regs[MODE]);
	write_c0_brcm_edsp(ctx->cp0_regs[EDSP]);
	write_c0_brcm_bootvec(ctx->cp0_regs[BOOT_VEC]);
	write_c0_ebase(ctx->cp0_regs[EBASE]);
}

static void  brcmstb_pm_handshake(void)
{
	void __iomem *base = ctrl.aon_ctrl_base;

Annotation

Implementation Notes