drivers/soc/fsl/qe/qe_io.c

Source file repositories/reference/linux-study-clean/drivers/soc/fsl/qe/qe_io.c

File Facts

System
Linux kernel
Corpus path
drivers/soc/fsl/qe/qe_io.c
Extension
.c
Size
4805 bytes
Lines
187
Domain
Driver Families
Bucket
drivers/soc
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * arch/powerpc/sysdev/qe_lib/qe_io.c
 *
 * QE Parallel I/O ports configuration routines
 *
 * Copyright 2006 Freescale Semiconductor, Inc. All rights reserved.
 *
 * Author: Li Yang <LeoLi@freescale.com>
 * Based on code from Shlomi Gridish <gridish@freescale.com>
 */

#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/ioport.h>

#include <asm/io.h>
#include <soc/fsl/qe/qe.h>

#undef DEBUG

static struct qe_pio_regs __iomem *par_io;
static int num_par_io_ports = 0;

int par_io_init(struct device_node *np)
{
	struct resource res;
	int ret;
	u32 num_ports;

	/* Map Parallel I/O ports registers */
	ret = of_address_to_resource(np, 0, &res);
	if (ret)
		return ret;
	par_io = ioremap(res.start, resource_size(&res));
	if (!par_io)
		return -ENOMEM;

	if (!of_property_read_u32(np, "num-ports", &num_ports))
		num_par_io_ports = num_ports;

	return 0;
}

void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
			 int open_drain, int assignment, int has_irq)
{
	u32 pin_mask1bit;
	u32 pin_mask2bits;
	u32 new_mask2bits;
	u32 tmp_val;

	/* calculate pin location for single and 2 bits information */
	pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));

	/* Set open drain, if required */
	tmp_val = ioread32be(&par_io->cpodr);
	if (open_drain)
		iowrite32be(pin_mask1bit | tmp_val, &par_io->cpodr);
	else
		iowrite32be(~pin_mask1bit & tmp_val, &par_io->cpodr);

	/* define direction */
	tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
		ioread32be(&par_io->cpdir2) :
		ioread32be(&par_io->cpdir1);

	/* get all bits mask for 2 bit per port */
	pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -
				(pin % (QE_PIO_PINS / 2) + 1) * 2));

	/* Get the final mask we need for the right definition */
	new_mask2bits = (u32) (dir << (QE_PIO_PINS -
				(pin % (QE_PIO_PINS / 2) + 1) * 2));

	/* clear and set 2 bits mask */
	if (pin > (QE_PIO_PINS / 2) - 1) {
		iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir2);
		tmp_val &= ~pin_mask2bits;
		iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir2);
	} else {
		iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir1);
		tmp_val &= ~pin_mask2bits;
		iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir1);
	}
	/* define pin assignment */
	tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
		ioread32be(&par_io->cppar2) :

Annotation

Implementation Notes