drivers/soc/fsl/qe/tsa.c
Source file repositories/reference/linux-study-clean/drivers/soc/fsl/qe/tsa.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/soc/fsl/qe/tsa.c- Extension
.c- Size
- 32343 bytes
- Lines
- 1169
- Domain
- Driver Families
- Bucket
- drivers/soc
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
tsa.hdt-bindings/soc/cpm1-fsl,tsa.hdt-bindings/soc/qe-fsl,tsa.hlinux/bitfield.hlinux/clk.hlinux/io.hlinux/module.hlinux/of.hlinux/of_platform.hlinux/platform_device.hlinux/slab.hsoc/fsl/qe/ucc.h
Detected Declarations
struct tsa_entries_areastruct tsa_tdmstruct tsastruct tsa_serialenum tsa_versionfunction tsa_write32function tsa_write16function tsa_write8function tsa_read32function tsa_read16function tsa_clrbits32function tsa_clrbits16function tsa_clrsetbits32function tsa_is_qefunction tsa_qe_serial_get_numfunction tsa_serial_get_numfunction tsa_cpm1_serial_connectfunction tsa_qe_serial_connectfunction tsa_serial_connectfunction tsa_serial_disconnectfunction tsa_serial_get_infofunction tsa_cpm1_init_entries_areafunction tsa_qe_init_entries_areafunction tsa_init_entries_areafunction tsa_cpm1_serial_id2cselfunction tsa_cpm1_add_entryfunction tsa_qe_serial_id2cselfunction tsa_qe_add_entryfunction tsa_add_entryfunction tsa_of_parse_tdm_routefunction tsa_of_parse_tdm_rx_routefunction tsa_of_parse_tdm_tx_routefunction tsa_of_parse_tdmsfunction for_each_available_child_of_node_scopedfunction for_each_available_child_of_node_scopedfunction tsa_init_si_ramfunction tsa_cpm1_setupfunction tsa_qe_setupfunction tsa_setupfunction tsa_probefunction tsa_removefunction probefunction tsa_serial_putfunction devm_tsa_serial_releaseexport tsa_serial_get_numexport tsa_serial_connectexport tsa_serial_disconnectexport tsa_serial_get_info
Annotated Snippet
struct tsa_entries_area {
void __iomem *entries_start;
void __iomem *entries_next;
void __iomem *last_entry;
};
struct tsa_tdm {
bool is_enable;
struct clk *l1rclk_clk;
struct clk *l1rsync_clk;
struct clk *l1tclk_clk;
struct clk *l1tsync_clk;
u32 simode_tdm;
};
#define TSA_TDMA 0
#define TSA_TDMB 1
#define TSA_TDMC 2 /* QE implementation only */
#define TSA_TDMD 3 /* QE implementation only */
enum tsa_version {
TSA_CPM1 = 1, /* Avoid 0 value */
TSA_QE,
};
struct tsa {
struct device *dev;
void __iomem *si_regs;
void __iomem *si_ram;
resource_size_t si_ram_sz;
spinlock_t lock; /* Lock for read/modify/write sequence */
enum tsa_version version;
int tdms; /* TSA_TDMx ORed */
#if IS_ENABLED(CONFIG_QUICC_ENGINE)
struct tsa_tdm tdm[4]; /* TDMa, TDMb, TDMc and TDMd */
#else
struct tsa_tdm tdm[2]; /* TDMa and TDMb */
#endif
/* Same number of serials for CPM1 and QE:
* CPM1: NU, 3 SCCs and 2 SMCs
* QE: NU and 5 UCCs
*/
struct tsa_serial {
unsigned int id;
struct tsa_serial_info info;
} serials[6];
};
static inline struct tsa *tsa_serial_get_tsa(struct tsa_serial *tsa_serial)
{
/* The serials table is indexed by the serial id */
return container_of(tsa_serial, struct tsa, serials[tsa_serial->id]);
}
static inline void tsa_write32(void __iomem *addr, u32 val)
{
iowrite32be(val, addr);
}
static inline void tsa_write16(void __iomem *addr, u16 val)
{
iowrite16be(val, addr);
}
static inline void tsa_write8(void __iomem *addr, u8 val)
{
iowrite8(val, addr);
}
static inline u32 tsa_read32(void __iomem *addr)
{
return ioread32be(addr);
}
static inline u16 tsa_read16(void __iomem *addr)
{
return ioread16be(addr);
}
static inline void tsa_clrbits32(void __iomem *addr, u32 clr)
{
tsa_write32(addr, tsa_read32(addr) & ~clr);
}
static inline void tsa_clrbits16(void __iomem *addr, u16 clr)
{
tsa_write16(addr, tsa_read16(addr) & ~clr);
}
static inline void tsa_clrsetbits32(void __iomem *addr, u32 clr, u32 set)
Annotation
- Immediate include surface: `tsa.h`, `dt-bindings/soc/cpm1-fsl,tsa.h`, `dt-bindings/soc/qe-fsl,tsa.h`, `linux/bitfield.h`, `linux/clk.h`, `linux/io.h`, `linux/module.h`, `linux/of.h`.
- Detected declarations: `struct tsa_entries_area`, `struct tsa_tdm`, `struct tsa`, `struct tsa_serial`, `enum tsa_version`, `function tsa_write32`, `function tsa_write16`, `function tsa_write8`, `function tsa_read32`, `function tsa_read16`.
- Atlas domain: Driver Families / drivers/soc.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.