drivers/soc/mediatek/mtk-mmsys.h

Source file repositories/reference/linux-study-clean/drivers/soc/mediatek/mtk-mmsys.h

File Facts

System
Linux kernel
Corpus path
drivers/soc/mediatek/mtk-mmsys.h
Extension
.h
Size
10764 bytes
Lines
322
Domain
Driver Families
Bucket
drivers/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct mtk_mmsys_routes {
	u32 from_comp;
	u32 to_comp;
	u32 addr;
	u32 mask;
	u32 val;
};

/**
 * struct mtk_mmsys_driver_data - Settings of the mmsys
 * @clk_driver: Clock driver name that the mmsys is using
 *              (defined in drivers/clk/mediatek/clk-*.c).
 * @routes: Routing table of the mmsys.
 *          It provides mux settings from one module to another.
 * @num_routes: Array size of the routes.
 * @sw0_rst_offset: Register offset for the reset control.
 * @num_resets: Number of reset bits that are defined
 * @is_vppsys: Whether the mmsys is VPPSYS (Video Processing Pipe)
 *             or VDOSYS (Video). Only VDOSYS needs to be added to drm driver.
 * @vsync_len: VSYNC length of the MIXER.
 *             VSYNC is usually triggered by the connector, so its length is a
 *             fixed value when the frame rate is decided, but ETHDR and
 *             MIXER generate their own VSYNC due to hardware design, therefore
 *             MIXER has to sync with ETHDR by adjusting VSYNC length.
 *             On MT8195, there is no such setting so we use the gap between
 *             falling edge and rising edge of SOF (Start of Frame) signal to
 *             do the job, but since MT8188, VSYNC_LEN setting is introduced to
 *             solve the problem and is given 0x40 (ticks) as the default value.
 *             Please notice that this value has to be set to 1 (minimum) if
 *             ETHDR is bypassed, otherwise MIXER could wait too long and causing
 *             underflow.
 *
 * Each MMSYS (multi-media system) may have different settings, they may use
 * different clock sources, mux settings, reset control ...etc., and these
 * differences are all stored here.
 */
struct mtk_mmsys_driver_data {
	const char *clk_driver;
	const struct mtk_mmsys_routes *routes;
	const unsigned int num_routes;
	const u16 sw0_rst_offset;
	const u8 *rst_tb;
	const u32 num_resets;
	const bool is_vppsys;
	const u8 vsync_len;
};

/*
 * Routes in mt2701 and mt2712 are different. That means
 * in the same register address, it controls different input/output
 * selection for each SoC. But, right now, they use the same table as
 * default routes meet their requirements. But we don't have the complete
 * route information for these three SoC, so just keep them in the same
 * table. After we've more information, we could separate mt2701, mt2712
 * to an independent table.
 */
static const struct mtk_mmsys_routes mmsys_default_routing_table[] = {
	{
		DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
		DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
		BLS_TO_DSI_RDMA1_TO_DPI1
	}, {
		DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
		DSI_SEL_IN_BLS
	}, {
		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
		DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
		BLS_TO_DPI_RDMA1_TO_DSI
	}, {
		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
		DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
		DSI_SEL_IN_RDMA
	}, {
		DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
		DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK,
		DPI_SEL_IN_BLS
	}, {
		DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
		DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1,
		GAMMA_MOUT_EN_RDMA1
	}, {
		DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0,
		OD_MOUT_EN_RDMA0
	}, {
		DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1,
		DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1,
		OD1_MOUT_EN_RDMA1
	}, {

Annotation

Implementation Notes