drivers/soc/microchip/mpfs-irqmux.c

Source file repositories/reference/linux-study-clean/drivers/soc/microchip/mpfs-irqmux.c

File Facts

System
Linux kernel
Corpus path
drivers/soc/microchip/mpfs-irqmux.c
Extension
.c
Size
5516 bytes
Lines
182
Domain
Driver Families
Bucket
drivers/soc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (direct_mode < 0) {
			of_node_put(imap_item.parent_args.np);
			return direct_mode;
		}

		line = imap_item.child_imap[0];
		gpio = line % 32;
		controller = line / 32;

		if (controller > 2) {
			of_node_put(imap_item.parent_args.np);
			dev_err(dev, "child interrupt number too large: %d\n", line);
			return -EINVAL;
		}

		if (test_and_set_bit(line, child_done)) {
			of_node_put(imap_item.parent_args.np);
			dev_err(dev, "mux child line %d already defined in interrupt-map\n",
				line);
			return -EINVAL;
		}

		parent_line = imap_item.parent_args.args[0] - MPFS_IRQMUX_DIRECT_START;
		if (direct_mode && test_and_set_bit(parent_line, parent_done)) {
			of_node_put(imap_item.parent_args.np);
			dev_err(dev, "mux parent line %d already defined in interrupt-map\n",
				line);
			return -EINVAL;
		}

		/*
		 * There are 41 interrupts assigned to GPIOs, of which 38 are "direct". Since the
		 * mux has 32 bits only, 6 of these exclusive/"direct" interrupts remain. These
		 * are used by GPIO controller 1's lines 18 to 23. Nothing needs to be done
		 * for these interrupts.
		 */
		if (controller == 1 && gpio >= 18)
			continue;

		/*
		 * The mux has a single register, where bits 0 to 13 mux between GPIO controller
		 * 1's 14 GPIOs and GPIO controller 2's first 14 GPIOs. The remaining bits mux
		 * between the first 18 GPIOs of controller 1 and the last 18 GPIOS of
		 * controller 2. If a bit in the mux's control register is set, the
		 * corresponding interrupt line for GPIO controller 0 or 1 will be put in
		 * "non-direct" mode. If cleared, the "fabric" controller's will.
		 *
		 * Register layout:
		 *    GPIO 1 interrupt line 17 | mux bit 31 | GPIO 2 interrupt line 31
		 *    ...                      | ...        | ...
		 *    ...                      | ...        | ...
		 *    GPIO 1 interrupt line  0 | mux bit 14 | GPIO 2 interrupt line 14
		 *    GPIO 0 interrupt line 13 | mux bit 13 | GPIO 2 interrupt line 13
		 *    ...                      | ...        | ...
		 *    ...                      | ...        | ...
		 *    GPIO 0 interrupt line  0 | mux bit  0 | GPIO 2 interrupt line  0
		 *
		 * As the binding mandates 70 items, one for each GPIO line, there's no need to
		 * handle anything for GPIO controller 2, since the bit will be set for the
		 * corresponding line in GPIO controller 0 or 1.
		 */
		if (controller == 2)
			continue;

		/*
		 * If in direct mode, the bit is cleared, nothing needs to be done as val is zero
		 * initialised and that's the direct mode setting for GPIO controller 0 and 1.
		 */
		if (direct_mode)
			continue;

		if (controller == 0)
			val |= 1U << gpio;
		else
			val |= 1U << (gpio + 14);
	}

	regmap_read(regmap, MPFS_IRQMUX_CR, &old);
	regmap_write(regmap, MPFS_IRQMUX_CR, val);

	if (val != old)
		dev_info(dev, "firmware mux setting of 0x%x overwritten to 0x%x\n", old, val);

	return 0;
}

static const struct of_device_id mpfs_irqmux_of_match[] = {
	{ .compatible = "microchip,mpfs-irqmux", },
	{ }
};

Annotation

Implementation Notes