drivers/soc/qcom/qcom-geni-se.c

Source file repositories/reference/linux-study-clean/drivers/soc/qcom/qcom-geni-se.c

File Facts

System
Linux kernel
Corpus path
drivers/soc/qcom/qcom-geni-se.c
Extension
.c
Size
51564 bytes
Lines
1686
Domain
Driver Families
Bucket
drivers/soc
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct geni_wrapper {
	struct device *dev;
	void __iomem *base;
	struct clk_bulk_data clks[MAX_CLKS];
	unsigned int num_clks;
};

/**
 * struct geni_se_desc - Data structure to represent the QUP Wrapper resources
 * @clks:		Name of the primary & optional secondary AHB clocks
 * @num_clks:		Count of clock names
 */
struct geni_se_desc {
	unsigned int num_clks;
	const char * const *clks;
};

static const char * const icc_path_names[] = {"qup-core", "qup-config",
						"qup-memory"};

static const char * const protocol_name[] = { "None", "SPI", "UART", "I2C", "I3C", "SPI SLAVE" };

/**
 * struct se_fw_hdr - Serial Engine firmware configuration header
 *
 * This structure defines the SE firmware header, which together with the
 * firmware payload is stored in individual ELF segments.
 *
 * @magic: Set to 'SEFW'.
 * @version: Structure version number.
 * @core_version: QUPV3 hardware version.
 * @serial_protocol: Encoded in GENI_FW_REVISION.
 * @fw_version: Firmware version, from GENI_FW_REVISION.
 * @cfg_version: Configuration version, from GENI_INIT_CFG_REVISION.
 * @fw_size_in_items: Number of 32-bit words in GENI_FW_RAM.
 * @fw_offset: Byte offset to GENI_FW_RAM array.
 * @cfg_size_in_items: Number of GENI_FW_CFG index/value pairs.
 * @cfg_idx_offset: Byte offset to GENI_FW_CFG index array.
 * @cfg_val_offset: Byte offset to GENI_FW_CFG values array.
 */
struct se_fw_hdr {
	__le32 magic;
	__le32 version;
	__le32 core_version;
	__le16 serial_protocol;
	__le16 fw_version;
	__le16 cfg_version;
	__le16 fw_size_in_items;
	__le16 fw_offset;
	__le16 cfg_size_in_items;
	__le16 cfg_idx_offset;
	__le16 cfg_val_offset;
};

/*Magic numbers*/
#define SE_MAGIC_NUM			0x57464553

#define MAX_GENI_CFG_RAMn_CNT		455

#define MI_PBT_NON_PAGED_SEGMENT	0x0
#define MI_PBT_HASH_SEGMENT		0x2
#define MI_PBT_NOTUSED_SEGMENT		0x3
#define MI_PBT_SHARED_SEGMENT		0x4

#define MI_PBT_FLAG_PAGE_MODE		BIT(20)
#define MI_PBT_FLAG_SEGMENT_TYPE	GENMASK(26, 24)
#define MI_PBT_FLAG_ACCESS_TYPE		GENMASK(23, 21)

#define MI_PBT_PAGE_MODE_VALUE(x) FIELD_GET(MI_PBT_FLAG_PAGE_MODE, x)

#define MI_PBT_SEGMENT_TYPE_VALUE(x) FIELD_GET(MI_PBT_FLAG_SEGMENT_TYPE, x)

#define MI_PBT_ACCESS_TYPE_VALUE(x) FIELD_GET(MI_PBT_FLAG_ACCESS_TYPE, x)

#define M_COMMON_GENI_M_IRQ_EN	(GENMASK(6, 1) | \
				M_IO_DATA_DEASSERT_EN | \
				M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \
				M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \
				M_TX_FIFO_WR_ERR_EN)

/* Common QUPV3 registers */
#define QUPV3_HW_VER_REG		0x4
#define QUPV3_SE_AHB_M_CFG		0x118
#define QUPV3_COMMON_CFG		0x120
#define QUPV3_COMMON_CGC_CTRL		0x21c

/* QUPV3_COMMON_CFG fields */
#define FAST_SWITCH_TO_HIGH_DISABLE	BIT(0)

/* QUPV3_SE_AHB_M_CFG fields */

Annotation

Implementation Notes