drivers/soc/tegra/fuse/speedo-tegra210.c
Source file repositories/reference/linux-study-clean/drivers/soc/tegra/fuse/speedo-tegra210.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/soc/tegra/fuse/speedo-tegra210.c- Extension
.c- Size
- 5132 bytes
- Lines
- 195
- Domain
- Driver Families
- Bucket
- drivers/soc
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/device.hlinux/kernel.hlinux/bug.hsoc/tegra/fuse.hfuse.h
Detected Declarations
function get_speedo_revisionfunction rev_sku_to_speedo_idsfunction get_process_idfunction tegra210_init_speedo_data
Annotated Snippet
switch (sku) {
case 0x00: /* Engineering SKU */
case 0x01: /* Engineering SKU */
case 0x13:
sku_info->cpu_speedo_id = 5;
sku_info->gpu_speedo_id = 2;
break;
case 0x07:
case 0x17:
case 0x1F:
sku_info->cpu_speedo_id = 7;
sku_info->gpu_speedo_id = 2;
break;
case 0x27:
sku_info->cpu_speedo_id = 1;
sku_info->gpu_speedo_id = 2;
break;
case 0x83:
sku_info->cpu_speedo_id = 3;
sku_info->gpu_speedo_id = 3;
break;
case 0x87:
sku_info->cpu_speedo_id = 2;
sku_info->gpu_speedo_id = 1;
break;
case 0x8F:
sku_info->soc_speedo_id = 2;
sku_info->cpu_speedo_id = 9;
sku_info->gpu_speedo_id = 2;
break;
default:
pr_err("Tegra210: unknown revision 2 or newer SKU %#04x\n", sku);
/* Using the default for the error case */
break;
}
} else if (sku == 0x00 || sku == 0x01 || sku == 0x07 || sku == 0x13 || sku == 0x17) {
sku_info->gpu_speedo_id = 1;
} else {
pr_err("Tegra210: unknown SKU %#04x\n", sku);
}
}
static int get_process_id(int value, const u32 *speedos, unsigned int num)
{
unsigned int i;
for (i = 0; i < num; i++)
if (value < speedos[i])
return i;
return -EINVAL;
}
void __init tegra210_init_speedo_data(struct tegra_sku_info *sku_info)
{
int cpu_speedo[3], soc_speedo[3];
unsigned int index;
u8 speedo_revision;
BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
THRESHOLD_INDEX_COUNT);
BUILD_BUG_ON(ARRAY_SIZE(gpu_process_speedos) !=
THRESHOLD_INDEX_COUNT);
BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
THRESHOLD_INDEX_COUNT);
/* Read speedo/IDDQ fuses */
cpu_speedo[0] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_0);
cpu_speedo[1] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_1);
cpu_speedo[2] = tegra_fuse_read_early(FUSE_CPU_SPEEDO_2);
soc_speedo[0] = tegra_fuse_read_early(FUSE_SOC_SPEEDO_0);
soc_speedo[1] = tegra_fuse_read_early(FUSE_SOC_SPEEDO_1);
soc_speedo[2] = tegra_fuse_read_early(FUSE_SOC_SPEEDO_2);
/*
* Determine CPU, GPU and SoC speedo values depending on speedo fusing
* revision. Note that GPU speedo value is fused in CPU_SPEEDO_2.
*/
speedo_revision = get_speedo_revision();
pr_info("Speedo Revision %u\n", speedo_revision);
if (speedo_revision >= 3) {
sku_info->cpu_speedo_value = cpu_speedo[0];
Annotation
- Immediate include surface: `linux/device.h`, `linux/kernel.h`, `linux/bug.h`, `soc/tegra/fuse.h`, `fuse.h`.
- Detected declarations: `function get_speedo_revision`, `function rev_sku_to_speedo_ids`, `function get_process_id`, `function tegra210_init_speedo_data`.
- Atlas domain: Driver Families / drivers/soc.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.