drivers/soundwire/qcom.c

Source file repositories/reference/linux-study-clean/drivers/soundwire/qcom.c

File Facts

System
Linux kernel
Corpus path
drivers/soundwire/qcom.c
Extension
.c
Size
53210 bytes
Lines
1839
Domain
Driver Families
Bucket
drivers/soundwire
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct qcom_swrm_port_config {
	u16 si;
	u8 off1;
	u8 off2;
	u8 bp_mode;
	u8 hstart;
	u8 hstop;
	u8 word_length;
	u8 blk_group_count;
	u8 lane_control;
};

/*
 * Internal IDs for different register layouts.  Only few registers differ per
 * each variant, so the list of IDs below does not include all of registers.
 */
enum {
	SWRM_REG_FRAME_GEN_ENABLED,
	SWRM_REG_INTERRUPT_STATUS,
	SWRM_REG_INTERRUPT_MASK_ADDR,
	SWRM_REG_INTERRUPT_CLEAR,
	SWRM_REG_INTERRUPT_CPU_EN,
	SWRM_REG_CMD_FIFO_WR_CMD,
	SWRM_REG_CMD_FIFO_RD_CMD,
	SWRM_REG_CMD_FIFO_STATUS,
	SWRM_REG_CMD_FIFO_RD_FIFO_ADDR,
	SWRM_OFFSET_DP_PORT_CTRL_BANK,
	SWRM_OFFSET_DP_PORT_CTRL_2_BANK,
	SWRM_OFFSET_DP_BLOCK_CTRL_1,
	SWRM_OFFSET_DP_BLOCK_CTRL2_BANK,
	SWRM_OFFSET_DP_PORT_HCTRL_BANK,
	SWRM_OFFSET_DP_BLOCK_CTRL3_BANK,
	SWRM_OFFSET_DP_SAMPLECTRL2_BANK,
};

struct qcom_swrm_ctrl {
	struct sdw_bus bus;
	struct device *dev;
	struct regmap *regmap;
	u32 max_reg;
	const unsigned int *reg_layout;
	void __iomem *mmio;
	struct reset_control *audio_cgcr;
#ifdef CONFIG_DEBUG_FS
	struct dentry *debugfs;
#endif
	struct completion broadcast;
	struct completion enumeration;
	/* Port alloc/free lock */
	struct mutex port_lock;
	struct clk *hclk;
	int irq;
	unsigned int version;
	int wake_irq;
	int num_din_ports;
	int num_dout_ports;
	int nports;
	int cols_index;
	int rows_index;
	unsigned long port_mask;
	u32 intr_mask;
	u8 rcmd_id;
	u8 wcmd_id;
	/* Port numbers are 1 - 14 */
	struct qcom_swrm_port_config *pconfig;
	struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
	enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
	int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
	int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
	u32 slave_status;
	u32 wr_fifo_depth;
	bool clock_stop_not_supported;
};

struct qcom_swrm_data {
	u32 default_cols;
	u32 default_rows;
	bool sw_clk_gate_required;
	u32 max_reg;
	const unsigned int *reg_layout;
};

static const unsigned int swrm_v1_3_reg_layout[] = {
	[SWRM_REG_FRAME_GEN_ENABLED] = SWRM_COMP_STATUS,
	[SWRM_REG_INTERRUPT_STATUS] = SWRM_V1_3_INTERRUPT_STATUS,
	[SWRM_REG_INTERRUPT_MASK_ADDR] = SWRM_V1_3_INTERRUPT_MASK_ADDR,
	[SWRM_REG_INTERRUPT_CLEAR] = SWRM_V1_3_INTERRUPT_CLEAR,
	[SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V1_3_INTERRUPT_CPU_EN,
	[SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V1_3_CMD_FIFO_WR_CMD,
	[SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V1_3_CMD_FIFO_RD_CMD,

Annotation

Implementation Notes