drivers/spi/spi-axi-spi-engine.c
Source file repositories/reference/linux-study-clean/drivers/spi/spi-axi-spi-engine.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/spi/spi-axi-spi-engine.c- Extension
.c- Size
- 37301 bytes
- Lines
- 1261
- Domain
- Driver Families
- Bucket
- drivers/spi
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/adi-axi-common.hlinux/bitfield.hlinux/bitops.hlinux/clk.hlinux/completion.hlinux/dmaengine.hlinux/interrupt.hlinux/io.hlinux/iopoll.hlinux/of.hlinux/module.hlinux/overflow.hlinux/platform_device.hlinux/spi/offload/provider.hlinux/spi/spi.htrace/events/spi.h
Detected Declarations
struct spi_engine_programstruct spi_engine_message_statestruct spi_engine_offloadstruct spi_enginefunction spi_engine_primary_lane_flagfunction spi_engine_all_lanes_flagsfunction spi_engine_program_add_cmdfunction spi_engine_get_configfunction spi_engine_gen_xferfunction spi_engine_gen_sleepfunction spi_engine_gen_csfunction __spi_validatefunction list_for_each_entryfunction spi_engine_compile_messagefunction list_for_each_entryfunction spi_engine_xfer_nextfunction spi_engine_tx_nextfunction spi_engine_rx_nextfunction spi_engine_write_cmd_fifofunction spi_engine_write_tx_fifofunction spi_engine_read_rx_fifofunction spi_engine_irqfunction spi_engine_offload_preparefunction list_for_each_entryfunction spi_engine_offload_unpreparefunction spi_engine_optimize_messagefunction spi_engine_unoptimize_messagefunction spi_engine_put_offloadfunction spi_engine_setupfunction spi_engine_transfer_one_messagefunction spi_engine_trigger_enablefunction spi_engine_trigger_disablefunction spi_engine_release_hwfunction spi_engine_probe
Annotated Snippet
struct spi_engine_program {
unsigned int length;
uint16_t instructions[] __counted_by(length);
};
/**
* struct spi_engine_message_state - SPI engine per-message state
*/
struct spi_engine_message_state {
/** @cmd_length: Number of elements in cmd_buf array. */
unsigned cmd_length;
/** @cmd_buf: Array of commands not yet written to CMD FIFO. */
const uint16_t *cmd_buf;
/** @tx_xfer: Next xfer with tx_buf not yet fully written to TX FIFO. */
struct spi_transfer *tx_xfer;
/** @tx_length: Size of tx_buf in bytes. */
unsigned int tx_length;
/** @tx_buf: Bytes not yet written to TX FIFO. */
const uint8_t *tx_buf;
/** @rx_xfer: Next xfer with rx_buf not yet fully written to RX FIFO. */
struct spi_transfer *rx_xfer;
/** @rx_length: Size of tx_buf in bytes. */
unsigned int rx_length;
/** @rx_buf: Bytes not yet written to the RX FIFO. */
uint8_t *rx_buf;
};
enum {
SPI_ENGINE_OFFLOAD_FLAG_ASSIGNED,
SPI_ENGINE_OFFLOAD_FLAG_PREPARED,
};
struct spi_engine_offload {
struct spi_engine *spi_engine;
unsigned long flags;
unsigned int offload_num;
unsigned int spi_mode_config;
unsigned int multi_lane_mode;
u8 rx_primary_lane_mask;
u8 tx_primary_lane_mask;
u8 rx_all_lanes_mask;
u8 tx_all_lanes_mask;
u8 bits_per_word;
};
struct spi_engine {
struct clk *clk;
struct clk *ref_clk;
spinlock_t lock;
void __iomem *base;
struct spi_engine_message_state msg_state;
struct completion msg_complete;
unsigned int int_enable;
/* shadows hardware CS inversion flag state */
u8 cs_inv;
unsigned int offload_ctrl_mem_size;
unsigned int offload_sdo_mem_size;
struct spi_offload *offload;
u32 offload_caps;
bool offload_requires_sync;
};
static void spi_engine_primary_lane_flag(struct spi_device *spi,
u8 *rx_lane_flags, u8 *tx_lane_flags)
{
*rx_lane_flags = BIT(spi->rx_lane_map[0]);
*tx_lane_flags = BIT(spi->tx_lane_map[0]);
}
static void spi_engine_all_lanes_flags(struct spi_device *spi,
u8 *rx_lane_flags, u8 *tx_lane_flags)
{
int i;
for (i = 0; i < spi->num_rx_lanes; i++)
*rx_lane_flags |= BIT(spi->rx_lane_map[i]);
for (i = 0; i < spi->num_tx_lanes; i++)
*tx_lane_flags |= BIT(spi->tx_lane_map[i]);
}
static void spi_engine_program_add_cmd(struct spi_engine_program *p,
bool dry, uint16_t cmd)
{
p->length++;
if (!dry)
Annotation
- Immediate include surface: `linux/adi-axi-common.h`, `linux/bitfield.h`, `linux/bitops.h`, `linux/clk.h`, `linux/completion.h`, `linux/dmaengine.h`, `linux/interrupt.h`, `linux/io.h`.
- Detected declarations: `struct spi_engine_program`, `struct spi_engine_message_state`, `struct spi_engine_offload`, `struct spi_engine`, `function spi_engine_primary_lane_flag`, `function spi_engine_all_lanes_flags`, `function spi_engine_program_add_cmd`, `function spi_engine_get_config`, `function spi_engine_gen_xfer`, `function spi_engine_gen_sleep`.
- Atlas domain: Driver Families / drivers/spi.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.