drivers/spi/spi-cavium.c

File Facts

System

Linux kernel

Corpus path

drivers/spi/spi-cavium.c

Extension

.c

Size

3606 bytes

Lines

151

Domain

Driver Families

Bucket

drivers/spi

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/spi/spi.h
• linux/module.h
• linux/delay.h
• linux/io.h
• spi-cavium.h

Detected Declarations

• function Copyright
• function octeon_spi_do_transfer
• function octeon_spi_transfer_one_message
• function list_for_each_entry

Annotated Snippet

if (r < 0) {
			status = r;
			goto err;
		}
		total_len += r;
	}
err:
	msg->status = status;
	msg->actual_length = total_len;
	spi_finalize_current_message(ctlr);
	return status;
}

Annotation

• Immediate include surface: `linux/spi/spi.h`, `linux/module.h`, `linux/delay.h`, `linux/io.h`, `spi-cavium.h`.
• Detected declarations: `function Copyright`, `function octeon_spi_do_transfer`, `function octeon_spi_transfer_one_message`, `function list_for_each_entry`.
• Atlas domain: Driver Families / drivers/spi.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.