drivers/spi/spi-npcm-fiu.c

Source file repositories/reference/linux-study-clean/drivers/spi/spi-npcm-fiu.c

File Facts

System
Linux kernel
Corpus path
drivers/spi/spi-npcm-fiu.c
Extension
.c
Size
22073 bytes
Lines
765
Domain
Driver Families
Bucket
drivers/spi
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct npcm_fiu_info {
	char *name;
	u32 fiu_id;
	u32 max_map_size;
	u32 max_cs;
};

struct fiu_data {
	const struct npcm_fiu_info *npcm_fiu_data_info;
	int fiu_max;
};

static const struct npcm_fiu_info npcm7xx_fiu_info[] = {
	{.name = "FIU0", .fiu_id = FIU0,
		.max_map_size = MAP_SIZE_128MB, .max_cs = 2},
	{.name = "FIU3", .fiu_id = FIU3,
		.max_map_size = MAP_SIZE_128MB, .max_cs = 4},
	{.name = "FIUX", .fiu_id = FIUX,
		.max_map_size = MAP_SIZE_16MB, .max_cs = 2} };

static const struct fiu_data npcm7xx_fiu_data = {
	.npcm_fiu_data_info = npcm7xx_fiu_info,
	.fiu_max = 3,
};

static const struct npcm_fiu_info npxm8xx_fiu_info[] = {
	{.name = "FIU0", .fiu_id = FIU0,
		.max_map_size = MAP_SIZE_128MB, .max_cs = 2},
	{.name = "FIU3", .fiu_id = FIU3,
		.max_map_size = MAP_SIZE_128MB, .max_cs = 4},
	{.name = "FIUX", .fiu_id = FIUX,
		.max_map_size = MAP_SIZE_16MB, .max_cs = 2},
	{.name = "FIU1", .fiu_id = FIU1,
		.max_map_size = MAP_SIZE_16MB, .max_cs = 4} };

static const struct fiu_data npxm8xx_fiu_data = {
	.npcm_fiu_data_info = npxm8xx_fiu_info,
	.fiu_max = 4,
};

struct npcm_fiu_spi;

struct npcm_fiu_chip {
	void __iomem *flash_region_mapped_ptr;
	struct npcm_fiu_spi *fiu;
	unsigned long clkrate;
	u32 chipselect;
};

struct npcm_fiu_spi {
	struct npcm_fiu_chip chip[NPCM_MAX_CHIP_NUM];
	const struct npcm_fiu_info *info;
	struct spi_mem_op drd_op;
	struct resource *res_mem;
	struct regmap *regmap;
	unsigned long clkrate;
	struct device *dev;
	struct clk *clk;
	bool spix_mode;
};

static const struct regmap_config npcm_mtd_regmap_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,
	.max_register = NPCM_FIU_MAX_REG_LIMIT,
};

static void npcm_fiu_set_drd(struct npcm_fiu_spi *fiu,
			     const struct spi_mem_op *op)
{
	regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
			   NPCM_FIU_DRD_CFG_ACCTYPE,
			   ilog2(op->addr.buswidth) <<
			   NPCM_FIU_DRD_ACCTYPE_SHIFT);
	fiu->drd_op.addr.buswidth = op->addr.buswidth;
	regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
			   NPCM_FIU_DRD_CFG_DBW,
			   op->dummy.nbytes << NPCM_FIU_DRD_DBW_SHIFT);
	fiu->drd_op.dummy.nbytes = op->dummy.nbytes;
	regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
			   NPCM_FIU_DRD_CFG_RDCMD, op->cmd.opcode);
	fiu->drd_op.cmd.opcode = op->cmd.opcode;
	regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
			   NPCM_FIU_DRD_CFG_ADDSIZ,
			   (op->addr.nbytes - 3) << NPCM_FIU_DRD_ADDSIZ_SHIFT);
	fiu->drd_op.addr.nbytes = op->addr.nbytes;
}

static ssize_t npcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc,

Annotation

Implementation Notes