drivers/spi/spi-pxa2xx.c
Source file repositories/reference/linux-study-clean/drivers/spi/spi-pxa2xx.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/spi/spi-pxa2xx.c- Extension
.c- Size
- 39785 bytes
- Lines
- 1540
- Domain
- Driver Families
- Bucket
- drivers/spi
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/atomic.hlinux/bitops.hlinux/bug.hlinux/clk.hlinux/delay.hlinux/device.hlinux/dmaengine.hlinux/err.hlinux/gpio/consumer.hlinux/interrupt.hlinux/io.hlinux/ioport.hlinux/math64.hlinux/minmax.hlinux/module.hlinux/pm_runtime.hlinux/property.hlinux/slab.hlinux/types.hlinux/spi/spi.hinternals.hspi-pxa2xx.h
Detected Declarations
struct chip_datastruct lpss_configfunction is_lpss_sspfunction is_quark_x1000_sspfunction is_mmp2_sspfunction is_mrfld_sspfunction pxa2xx_spi_updatefunction pxa2xx_spi_get_ssrc1_change_maskfunction pxa2xx_spi_get_rx_default_threfunction pxa2xx_spi_txfifo_fullfunction pxa2xx_spi_clear_rx_threfunction pxa2xx_spi_set_rx_threfunction pxa2xx_configure_sscr0function is_lpss_sspfunction __lpss_ssp_write_privfunction __lpss_ssp_update_privfunction lpss_ssp_setupfunction lpss_ssp_select_csfunction lpss_ssp_cs_controlfunction cs_assertfunction cs_deassertfunction pxa2xx_spi_set_csfunction pxa2xx_spi_flushfunction pxa2xx_spi_offfunction null_writerfunction null_readerfunction u8_writerfunction u8_readerfunction u16_writerfunction u16_readerfunction u32_writerfunction u32_readerfunction reset_sccr1function int_stop_and_resetfunction int_error_stopfunction int_transfer_completefunction interrupt_transferfunction handle_bad_msgfunction ssp_intfunction registerfunction ssp_get_clk_divfunction pxa2xx_ssp_get_clk_divfunction pxa2xx_spi_can_dmafunction pxa2xx_spi_transfer_onefunction pxa2xx_spi_target_abortfunction pxa2xx_spi_handle_errfunction pxa2xx_spi_unprepare_transferfunction setup
Annotated Snippet
struct chip_data {
u32 cr1;
u32 dds_rate;
u32 threshold;
u16 lpss_rx_threshold;
u16 lpss_tx_threshold;
};
#define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
#define LPSS_CS_CONTROL_SW_MODE BIT(0)
#define LPSS_CS_CONTROL_CS_HIGH BIT(1)
#define LPSS_CAPS_CS_EN_SHIFT 9
#define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
#define LPSS_PRIV_CLOCK_GATE 0x38
#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3
#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3
#define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_OFF 0x0
struct lpss_config {
/* LPSS offset from drv_data->ioaddr */
unsigned offset;
/* Register offsets from drv_data->lpss_base or -1 */
int reg_general;
int reg_ssp;
int reg_cs_ctrl;
int reg_capabilities;
/* FIFO thresholds */
u32 rx_threshold;
u32 tx_threshold_lo;
u32 tx_threshold_hi;
/* Chip select control */
unsigned cs_sel_shift;
unsigned cs_sel_mask;
/* Quirks */
unsigned cs_clk_stays_gated : 1;
};
/* Keep these sorted with enum pxa_ssp_type */
static const struct lpss_config lpss_platforms[] = {
{ /* LPSS_LPT_SSP */
.offset = 0x800,
.reg_general = 0x08,
.reg_ssp = 0x0c,
.reg_cs_ctrl = 0x18,
.reg_capabilities = -1,
.rx_threshold = 64,
.tx_threshold_lo = 160,
.tx_threshold_hi = 224,
},
{ /* LPSS_BYT_SSP */
.offset = 0x400,
.reg_general = 0x08,
.reg_ssp = 0x0c,
.reg_cs_ctrl = 0x18,
.reg_capabilities = -1,
.rx_threshold = 64,
.tx_threshold_lo = 160,
.tx_threshold_hi = 224,
},
{ /* LPSS_BSW_SSP */
.offset = 0x400,
.reg_general = 0x08,
.reg_ssp = 0x0c,
.reg_cs_ctrl = 0x18,
.reg_capabilities = -1,
.rx_threshold = 64,
.tx_threshold_lo = 160,
.tx_threshold_hi = 224,
.cs_sel_shift = 2,
.cs_sel_mask = 1 << 2,
},
{ /* LPSS_SPT_SSP */
.offset = 0x200,
.reg_general = -1,
.reg_ssp = 0x20,
.reg_cs_ctrl = 0x24,
.reg_capabilities = -1,
.rx_threshold = 1,
.tx_threshold_lo = 32,
.tx_threshold_hi = 56,
},
{ /* LPSS_BXT_SSP */
.offset = 0x200,
.reg_general = -1,
.reg_ssp = 0x20,
.reg_cs_ctrl = 0x24,
.reg_capabilities = 0xfc,
.rx_threshold = 1,
.tx_threshold_lo = 16,
Annotation
- Immediate include surface: `linux/atomic.h`, `linux/bitops.h`, `linux/bug.h`, `linux/clk.h`, `linux/delay.h`, `linux/device.h`, `linux/dmaengine.h`, `linux/err.h`.
- Detected declarations: `struct chip_data`, `struct lpss_config`, `function is_lpss_ssp`, `function is_quark_x1000_ssp`, `function is_mmp2_ssp`, `function is_mrfld_ssp`, `function pxa2xx_spi_update`, `function pxa2xx_spi_get_ssrc1_change_mask`, `function pxa2xx_spi_get_rx_default_thre`, `function pxa2xx_spi_txfifo_full`.
- Atlas domain: Driver Families / drivers/spi.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.