drivers/spi/spi-sh-msiof.c
Source file repositories/reference/linux-study-clean/drivers/spi/spi-sh-msiof.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/spi/spi-sh-msiof.c- Extension
.c- Size
- 34205 bytes
- Lines
- 1350
- Domain
- Driver Families
- Bucket
- drivers/spi
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitmap.hlinux/clk.hlinux/completion.hlinux/delay.hlinux/dma-mapping.hlinux/dmaengine.hlinux/err.hlinux/interrupt.hlinux/io.hlinux/iopoll.hlinux/kernel.hlinux/module.hlinux/of.hlinux/of_graph.hlinux/platform_device.hlinux/pm_runtime.hlinux/sh_dma.hlinux/spi/sh_msiof.hlinux/spi/spi.hlinux/unaligned.h
Detected Declarations
struct sh_msiof_chipdatastruct sh_msiof_spi_privfunction sh_msiof_readfunction sh_msiof_writefunction sh_msiof_modify_ctr_waitfunction sh_msiof_spi_irqfunction sh_msiof_spi_reset_regsfunction sh_msiof_spi_set_clk_regsfunction sh_msiof_get_delay_bitfunction sh_msiof_spi_get_dtdl_and_syncdlfunction sh_msiof_spi_set_pin_regsfunction sh_msiof_spi_set_mode_regsfunction sh_msiof_reset_strfunction sh_msiof_spi_write_fifo_8function sh_msiof_spi_write_fifo_16function sh_msiof_spi_write_fifo_16ufunction sh_msiof_spi_write_fifo_32function sh_msiof_spi_write_fifo_32ufunction sh_msiof_spi_write_fifo_s32function sh_msiof_spi_write_fifo_s32ufunction sh_msiof_spi_read_fifo_8function sh_msiof_spi_read_fifo_16function sh_msiof_spi_read_fifo_16ufunction sh_msiof_spi_read_fifo_32function sh_msiof_spi_read_fifo_32ufunction sh_msiof_spi_read_fifo_s32function sh_msiof_spi_read_fifo_s32ufunction sh_msiof_spi_setupfunction sh_msiof_prepare_messagefunction sh_msiof_spi_startfunction sh_msiof_spi_stopfunction sh_msiof_target_abortfunction sh_msiof_wait_for_completionfunction sh_msiof_spi_txrx_oncefunction sh_msiof_dma_completefunction sh_msiof_dma_oncefunction copy_bswap32function copy_wswap32function copy_plain32function sh_msiof_transfer_onefunction sh_msiof_request_dmafunction sh_msiof_release_dmafunction sh_msiof_spi_probefunction sh_msiof_spi_removefunction sh_msiof_spi_suspendfunction sh_msiof_spi_resume
Annotated Snippet
struct sh_msiof_chipdata {
u32 bits_per_word_mask;
u16 tx_fifo_size;
u16 rx_fifo_size;
u16 ctlr_flags;
u16 min_div_pow;
u32 flags;
};
struct sh_msiof_spi_priv {
struct spi_controller *ctlr;
void __iomem *mapbase;
struct clk *clk;
struct platform_device *pdev;
struct sh_msiof_spi_info *info;
struct completion done;
struct completion done_txdma;
unsigned int tx_fifo_size;
unsigned int rx_fifo_size;
unsigned int min_div_pow;
void *tx_dma_page;
void *rx_dma_page;
dma_addr_t tx_dma_addr;
dma_addr_t rx_dma_addr;
bool native_cs_inited;
bool native_cs_high;
bool target_aborted;
};
#define MAX_SS 3 /* Maximum number of native chip selects */
static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
{
switch (reg_offs) {
case SITSCR:
case SIRSCR:
return ioread16(p->mapbase + reg_offs);
default:
return ioread32(p->mapbase + reg_offs);
}
}
static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
u32 value)
{
switch (reg_offs) {
case SITSCR:
case SIRSCR:
iowrite16(value, p->mapbase + reg_offs);
break;
default:
iowrite32(value, p->mapbase + reg_offs);
break;
}
}
static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
u32 clr, u32 set)
{
u32 mask = clr | set;
u32 data;
data = sh_msiof_read(p, SICTR);
data &= ~clr;
data |= set;
sh_msiof_write(p, SICTR, data);
return readl_poll_timeout_atomic(p->mapbase + SICTR, data,
(data & mask) == set, 1, 100);
}
static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
{
struct sh_msiof_spi_priv *p = data;
/* just disable the interrupt and wake up */
sh_msiof_write(p, SIIER, 0);
complete(&p->done);
return IRQ_HANDLED;
}
static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p)
{
u32 mask = SICTR_TXRST | SICTR_RXRST;
u32 data;
data = sh_msiof_read(p, SICTR);
data |= mask;
sh_msiof_write(p, SICTR, data);
Annotation
- Immediate include surface: `linux/bitmap.h`, `linux/clk.h`, `linux/completion.h`, `linux/delay.h`, `linux/dma-mapping.h`, `linux/dmaengine.h`, `linux/err.h`, `linux/interrupt.h`.
- Detected declarations: `struct sh_msiof_chipdata`, `struct sh_msiof_spi_priv`, `function sh_msiof_read`, `function sh_msiof_write`, `function sh_msiof_modify_ctr_wait`, `function sh_msiof_spi_irq`, `function sh_msiof_spi_reset_regs`, `function sh_msiof_spi_set_clk_regs`, `function sh_msiof_get_delay_bit`, `function sh_msiof_spi_get_dtdl_and_syncdl`.
- Atlas domain: Driver Families / drivers/spi.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.