drivers/spi/spi-stm32.c
Source file repositories/reference/linux-study-clean/drivers/spi/spi-stm32.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/spi/spi-stm32.c- Extension
.c- Size
- 79571 bytes
- Lines
- 2676
- Domain
- Driver Families
- Bucket
- drivers/spi
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitfield.hlinux/debugfs.hlinux/clk.hlinux/delay.hlinux/dma-mapping.hlinux/dmaengine.hlinux/genalloc.hlinux/interrupt.hlinux/iopoll.hlinux/module.hlinux/of.hlinux/platform_device.hlinux/pinctrl/consumer.hlinux/pm_runtime.hlinux/reset.hlinux/spi/spi.h
Detected Declarations
struct stm32_spi_regstruct stm32_spi_regspecstruct stm32_spistruct stm32_spi_cfgstruct stm32_spifunction stm32_spi_set_bitsfunction stm32_spi_clr_bitsfunction stm32h7_spi_get_fifo_sizefunction stm32f4_spi_get_bpw_maskfunction stm32f7_spi_get_bpw_maskfunction stm32h7_spi_get_bpw_maskfunction stm32mp25_spi_get_bpw_maskfunction stm32_spi_prepare_mbrfunction stm32h7_spi_prepare_fthlvfunction stm32f4_spi_write_txfunction stm32f7_spi_write_txfunction stm32h7_spi_write_txfifofunction stm32f4_spi_read_rxfunction stm32f7_spi_read_rxfunction stm32h7_spi_read_rxfifofunction stm32_spi_enablefunction stm32fx_spi_disablefunction stm32h7_spi_disablefunction stm32_spi_can_dmafunction stm32fx_spi_irq_eventfunction stm32fx_spi_irq_threadfunction stm32h7_spi_irq_threadfunction stm32_spi_optimize_messagefunction stm32_spi_prepare_msgfunction stm32fx_spi_dma_tx_cbfunction stm32_spi_dma_rx_cbfunction stm32_spi_dma_configfunction stm32fx_spi_transfer_one_irqfunction stm32h7_spi_transfer_one_pollfunction stm32h7_spi_transfer_one_irqfunction stm32fx_spi_transfer_one_dma_startfunction stm32f7_spi_transfer_one_dma_startfunction stm32h7_spi_transfer_one_dma_startfunction stm32_spi_prepare_rx_dma_mdma_chainingfunction stm32_spi_transfer_one_dmafunction stm32f4_spi_set_bpwfunction stm32f7_spi_set_bpwfunction stm32h7_spi_set_bpwfunction stm32_spi_set_mbrfunction stm32_spi_communication_typefunction stm32fx_spi_set_modefunction stm32h7_spi_set_modefunction stm32h7_spi_data_idleness
Annotated Snippet
struct stm32_spi_reg {
int reg;
int mask;
int shift;
};
/**
* struct stm32_spi_regspec - stm32 registers definition, compatible dependent data
* @en: enable register and SPI enable bit
* @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit
* @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit
* @cpol: clock polarity register and polarity bit
* @cpha: clock phase register and phase bit
* @lsb_first: LSB transmitted first register and bit
* @cs_high: chips select active value
* @br: baud rate register and bitfields
* @rx: SPI RX data register
* @tx: SPI TX data register
* @fullcfg: SPI full or limited feature set register
* @rdy_en: SPI ready feature register
*/
struct stm32_spi_regspec {
const struct stm32_spi_reg en;
const struct stm32_spi_reg dma_rx_en;
const struct stm32_spi_reg dma_tx_en;
const struct stm32_spi_reg cpol;
const struct stm32_spi_reg cpha;
const struct stm32_spi_reg lsb_first;
const struct stm32_spi_reg cs_high;
const struct stm32_spi_reg br;
const struct stm32_spi_reg rx;
const struct stm32_spi_reg tx;
const struct stm32_spi_reg fullcfg;
const struct stm32_spi_reg rdy_en;
};
struct stm32_spi;
/**
* struct stm32_spi_cfg - stm32 compatible configuration data
* @regs: registers descriptions
* @get_fifo_size: routine to get fifo size
* @get_bpw_mask: routine to get bits per word mask
* @disable: routine to disable controller
* @config: routine to configure controller as SPI Host
* @set_bpw: routine to configure registers to for bits per word
* @set_mode: routine to configure registers to desired mode
* @set_data_idleness: optional routine to configure registers to desired idle
* time between frames (if driver has this functionality)
* @set_number_of_data: optional routine to configure registers to desired
* number of data (if driver has this functionality)
* @write_tx: routine to write to transmit register/FIFO
* @read_rx: routine to read from receive register/FIFO
* @transfer_one_dma_start: routine to start transfer a single spi_transfer
* using DMA
* @dma_rx_cb: routine to call after DMA RX channel operation is complete
* @dma_tx_cb: routine to call after DMA TX channel operation is complete
* @transfer_one_irq: routine to configure interrupts for driver
* @transfer_one_poll: routine to perform a transfer via register polling
* @irq_handler_event: Interrupt handler for SPI controller events
* @irq_handler_thread: thread of interrupt handler for SPI controller
* @baud_rate_div_min: minimum baud rate divisor
* @baud_rate_div_max: maximum baud rate divisor
* @has_fifo: boolean to know if fifo is used for driver
* @has_device_mode: is this compatible capable to switch on device mode
* @flags: compatible specific SPI controller flags used at registration time
* @prevent_dma_burst: boolean to indicate to prevent DMA burst
*/
struct stm32_spi_cfg {
const struct stm32_spi_regspec *regs;
int (*get_fifo_size)(struct stm32_spi *spi);
int (*get_bpw_mask)(struct stm32_spi *spi);
void (*disable)(struct stm32_spi *spi);
int (*config)(struct stm32_spi *spi);
void (*set_bpw)(struct stm32_spi *spi);
int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
void (*set_data_idleness)(struct stm32_spi *spi, struct spi_transfer *xfer);
int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
void (*write_tx)(struct stm32_spi *spi);
void (*read_rx)(struct stm32_spi *spi);
void (*transfer_one_dma_start)(struct stm32_spi *spi);
void (*dma_rx_cb)(void *data);
void (*dma_tx_cb)(void *data);
int (*transfer_one_irq)(struct stm32_spi *spi);
int (*transfer_one_poll)(struct stm32_spi *spi);
irqreturn_t (*irq_handler_event)(int irq, void *dev_id);
irqreturn_t (*irq_handler_thread)(int irq, void *dev_id);
unsigned int baud_rate_div_min;
unsigned int baud_rate_div_max;
bool has_fifo;
Annotation
- Immediate include surface: `linux/bitfield.h`, `linux/debugfs.h`, `linux/clk.h`, `linux/delay.h`, `linux/dma-mapping.h`, `linux/dmaengine.h`, `linux/genalloc.h`, `linux/interrupt.h`.
- Detected declarations: `struct stm32_spi_reg`, `struct stm32_spi_regspec`, `struct stm32_spi`, `struct stm32_spi_cfg`, `struct stm32_spi`, `function stm32_spi_set_bits`, `function stm32_spi_clr_bits`, `function stm32h7_spi_get_fifo_size`, `function stm32f4_spi_get_bpw_mask`, `function stm32f7_spi_get_bpw_mask`.
- Atlas domain: Driver Families / drivers/spi.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.