drivers/spi/spi-synquacer.c
Source file repositories/reference/linux-study-clean/drivers/spi/spi-synquacer.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/spi/spi-synquacer.c- Extension
.c- Size
- 22253 bytes
- Lines
- 822
- Domain
- Driver Families
- Bucket
- drivers/spi
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/acpi.hlinux/delay.hlinux/interrupt.hlinux/io.hlinux/module.hlinux/of.hlinux/platform_device.hlinux/pm_runtime.hlinux/scatterlist.hlinux/slab.hlinux/spi/spi.hlinux/spinlock.hlinux/clk.h
Detected Declarations
struct synquacer_spifunction read_fifofunction write_fifofunction synquacer_spi_configfunction synquacer_spi_transfer_onefunction synquacer_spi_set_csfunction synquacer_spi_wait_status_updatefunction synquacer_spi_enablefunction sq_spi_rx_handlerfunction sq_spi_tx_handlerfunction synquacer_spi_probefunction synquacer_spi_removefunction synquacer_spi_suspendfunction synquacer_spi_resume
Annotated Snippet
struct synquacer_spi {
struct device *dev;
struct completion transfer_done;
unsigned int cs;
unsigned int bpw;
unsigned int mode;
unsigned int speed;
bool aces, rtm;
void *rx_buf;
const void *tx_buf;
struct clk *clk;
int clk_src_type;
void __iomem *regs;
u32 tx_words, rx_words;
unsigned int bus_width;
unsigned int transfer_mode;
char rx_irq_name[SYNQUACER_HSSPI_IRQ_NAME_MAX];
char tx_irq_name[SYNQUACER_HSSPI_IRQ_NAME_MAX];
};
static int read_fifo(struct synquacer_spi *sspi)
{
u32 len = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTATUS);
len = (len >> SYNQUACER_HSSPI_DMSTATUS_RX_DATA_SHIFT) &
SYNQUACER_HSSPI_DMSTATUS_RX_DATA_MASK;
len = min(len, sspi->rx_words);
switch (sspi->bpw) {
case 8: {
u8 *buf = sspi->rx_buf;
ioread8_rep(sspi->regs + SYNQUACER_HSSPI_REG_RX_FIFO,
buf, len);
sspi->rx_buf = buf + len;
break;
}
case 16: {
u16 *buf = sspi->rx_buf;
ioread16_rep(sspi->regs + SYNQUACER_HSSPI_REG_RX_FIFO,
buf, len);
sspi->rx_buf = buf + len;
break;
}
case 24:
/* fallthrough, should use 32-bits access */
case 32: {
u32 *buf = sspi->rx_buf;
ioread32_rep(sspi->regs + SYNQUACER_HSSPI_REG_RX_FIFO,
buf, len);
sspi->rx_buf = buf + len;
break;
}
default:
return -EINVAL;
}
sspi->rx_words -= len;
return 0;
}
static int write_fifo(struct synquacer_spi *sspi)
{
u32 len = readl(sspi->regs + SYNQUACER_HSSPI_REG_DMSTATUS);
len = (len >> SYNQUACER_HSSPI_DMSTATUS_TX_DATA_SHIFT) &
SYNQUACER_HSSPI_DMSTATUS_TX_DATA_MASK;
len = min(SYNQUACER_HSSPI_FIFO_DEPTH - len,
sspi->tx_words);
switch (sspi->bpw) {
case 8: {
const u8 *buf = sspi->tx_buf;
iowrite8_rep(sspi->regs + SYNQUACER_HSSPI_REG_TX_FIFO,
buf, len);
sspi->tx_buf = buf + len;
break;
}
case 16: {
const u16 *buf = sspi->tx_buf;
iowrite16_rep(sspi->regs + SYNQUACER_HSSPI_REG_TX_FIFO,
buf, len);
sspi->tx_buf = buf + len;
break;
}
case 24:
Annotation
- Immediate include surface: `linux/acpi.h`, `linux/delay.h`, `linux/interrupt.h`, `linux/io.h`, `linux/module.h`, `linux/of.h`, `linux/platform_device.h`, `linux/pm_runtime.h`.
- Detected declarations: `struct synquacer_spi`, `function read_fifo`, `function write_fifo`, `function synquacer_spi_config`, `function synquacer_spi_transfer_one`, `function synquacer_spi_set_cs`, `function synquacer_spi_wait_status_update`, `function synquacer_spi_enable`, `function sq_spi_rx_handler`, `function sq_spi_tx_handler`.
- Atlas domain: Driver Families / drivers/spi.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.