drivers/spi/spi-tegra20-slink.c
Source file repositories/reference/linux-study-clean/drivers/spi/spi-tegra20-slink.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/spi/spi-tegra20-slink.c- Extension
.c- Size
- 33631 bytes
- Lines
- 1220
- Domain
- Driver Families
- Bucket
- drivers/spi
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk.hlinux/completion.hlinux/delay.hlinux/dmaengine.hlinux/dma-mapping.hlinux/dmapool.hlinux/err.hlinux/interrupt.hlinux/io.hlinux/kernel.hlinux/kthread.hlinux/module.hlinux/platform_device.hlinux/pm_opp.hlinux/pm_runtime.hlinux/of.hlinux/reset.hlinux/spi/spi.hsoc/tegra/common.h
Detected Declarations
struct tegra_slink_chip_datastruct tegra_slink_datafunction tegra_slink_readlfunction tegra_slink_writelfunction tegra_slink_clear_statusfunction tegra_slink_get_packed_sizefunction tegra_slink_calculate_curr_xfer_paramfunction tegra_slink_fill_tx_fifo_from_client_txbuffunction tegra_slink_read_rx_fifo_to_client_rxbuffunction tegra_slink_copy_client_txbuf_to_spi_txbuffunction tegra_slink_copy_spi_rxbuf_to_client_rxbuffunction tegra_slink_dma_completefunction tegra_slink_start_tx_dmafunction tegra_slink_start_rx_dmafunction tegra_slink_start_dma_based_transferfunction tegra_slink_start_cpu_based_transferfunction tegra_slink_init_dma_paramfunction tegra_slink_deinit_dma_paramfunction tegra_slink_start_transfer_onefunction tegra_slink_setupfunction tegra_slink_prepare_messagefunction tegra_slink_transfer_onefunction tegra_slink_unprepare_messagefunction handle_cpu_based_xferfunction handle_dma_based_xferfunction tegra_slink_isr_threadfunction tegra_slink_isrfunction tegra_slink_probefunction tegra_slink_removefunction tegra_slink_suspendfunction tegra_slink_resumefunction tegra_slink_runtime_suspendfunction tegra_slink_runtime_resume
Annotated Snippet
struct tegra_slink_chip_data {
bool cs_hold_time;
};
struct tegra_slink_data {
struct device *dev;
struct spi_controller *host;
const struct tegra_slink_chip_data *chip_data;
spinlock_t lock;
struct clk *clk;
struct reset_control *rst;
void __iomem *base;
phys_addr_t phys;
unsigned irq;
u32 cur_speed;
struct spi_device *cur_spi;
unsigned cur_pos;
unsigned cur_len;
unsigned words_per_32bit;
unsigned bytes_per_word;
unsigned curr_dma_words;
unsigned cur_direction;
unsigned cur_rx_pos;
unsigned cur_tx_pos;
unsigned dma_buf_size;
unsigned max_buf_size;
bool is_curr_dma_xfer;
struct completion rx_dma_complete;
struct completion tx_dma_complete;
u32 tx_status;
u32 rx_status;
u32 status_reg;
bool is_packed;
u32 packed_size;
u32 command_reg;
u32 command2_reg;
u32 dma_control_reg;
u32 def_command_reg;
u32 def_command2_reg;
struct completion xfer_completion;
struct spi_transfer *curr_xfer;
struct dma_chan *rx_dma_chan;
u32 *rx_dma_buf;
dma_addr_t rx_dma_phys;
struct dma_async_tx_descriptor *rx_dma_desc;
struct dma_chan *tx_dma_chan;
u32 *tx_dma_buf;
dma_addr_t tx_dma_phys;
struct dma_async_tx_descriptor *tx_dma_desc;
};
static inline u32 tegra_slink_readl(struct tegra_slink_data *tspi,
unsigned long reg)
{
return readl(tspi->base + reg);
}
static inline void tegra_slink_writel(struct tegra_slink_data *tspi,
u32 val, unsigned long reg)
{
writel(val, tspi->base + reg);
/* Read back register to make sure that register writes completed */
if (reg != SLINK_TX_FIFO)
readl(tspi->base + SLINK_MAS_DATA);
}
static void tegra_slink_clear_status(struct tegra_slink_data *tspi)
{
u32 val_write;
tegra_slink_readl(tspi, SLINK_STATUS);
/* Write 1 to clear status register */
val_write = SLINK_RDY | SLINK_FIFO_ERROR;
tegra_slink_writel(tspi, val_write, SLINK_STATUS);
}
static u32 tegra_slink_get_packed_size(struct tegra_slink_data *tspi,
struct spi_transfer *t)
{
Annotation
- Immediate include surface: `linux/clk.h`, `linux/completion.h`, `linux/delay.h`, `linux/dmaengine.h`, `linux/dma-mapping.h`, `linux/dmapool.h`, `linux/err.h`, `linux/interrupt.h`.
- Detected declarations: `struct tegra_slink_chip_data`, `struct tegra_slink_data`, `function tegra_slink_readl`, `function tegra_slink_writel`, `function tegra_slink_clear_status`, `function tegra_slink_get_packed_size`, `function tegra_slink_calculate_curr_xfer_param`, `function tegra_slink_fill_tx_fifo_from_client_txbuf`, `function tegra_slink_read_rx_fifo_to_client_rxbuf`, `function tegra_slink_copy_client_txbuf_to_spi_txbuf`.
- Atlas domain: Driver Families / drivers/spi.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.