drivers/staging/media/atomisp/include/mmu/isp_mmu.h
Source file repositories/reference/linux-study-clean/drivers/staging/media/atomisp/include/mmu/isp_mmu.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/staging/media/atomisp/include/mmu/isp_mmu.h- Extension
.h- Size
- 4047 bytes
- Lines
- 159
- Domain
- Driver Families
- Bucket
- drivers/staging
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/types.hlinux/mutex.hlinux/slab.h
Detected Declarations
struct isp_mmustruct isp_mmu_clientstruct isp_mmufunction isp_mmu_flush_tlb_allfunction isp_mmu_flush_tlb_range
Annotated Snippet
struct isp_mmu_client {
/*
* const value
*
* @name:
* driver name
* @pte_valid_mask:
* should be 1 bit valid data, meaning the value should
* be power of 2.
*/
char *name;
unsigned int pte_valid_mask;
unsigned int null_pte;
/*
* get page directory base address (physical address).
*
* must be provided.
*/
unsigned int (*get_pd_base)(struct isp_mmu *mmu, phys_addr_t pd_base);
/*
* callback to flush tlb.
*
* tlb_flush_range will at least flush TLBs containing
* address mapping from addr to addr + size.
*
* tlb_flush_all will flush all TLBs.
*
* tlb_flush_all is must be provided. if tlb_flush_range is
* not valid, it will set to tlb_flush_all by default.
*/
void (*tlb_flush_range)(struct isp_mmu *mmu,
unsigned int addr, unsigned int size);
void (*tlb_flush_all)(struct isp_mmu *mmu);
unsigned int (*phys_to_pte)(struct isp_mmu *mmu,
phys_addr_t phys);
phys_addr_t (*pte_to_phys)(struct isp_mmu *mmu,
unsigned int pte);
};
struct isp_mmu {
struct isp_mmu_client *driver;
unsigned int l1_pte;
int l2_pgt_refcount[ISP_L1PT_PTES];
phys_addr_t base_address;
struct mutex pt_mutex;
};
/* flags for PDE and PTE */
#define ISP_PTE_VALID_MASK(mmu) \
((mmu)->driver->pte_valid_mask)
#define ISP_PTE_VALID(mmu, pte) \
((pte) & ISP_PTE_VALID_MASK(mmu))
#define NULL_PAGE ((phys_addr_t)(-1) & ISP_PAGE_MASK)
#define PAGE_VALID(page) ((page) != NULL_PAGE)
/*
* init mmu with specific mmu driver.
*/
int isp_mmu_init(struct isp_mmu *mmu, struct isp_mmu_client *driver);
/*
* cleanup all mmu related things.
*/
void isp_mmu_exit(struct isp_mmu *mmu);
/*
* setup/remove address mapping for pgnr continuous physical pages
* and isp_virt.
*
* map/unmap is mutex lock protected, and caller does not have
* to do lock/unlock operation.
*
* map/unmap will not flush tlb, and caller needs to deal with
* this itself.
*/
int isp_mmu_map(struct isp_mmu *mmu, unsigned int isp_virt,
phys_addr_t phys, unsigned int pgnr);
void isp_mmu_unmap(struct isp_mmu *mmu, unsigned int isp_virt,
unsigned int pgnr);
static inline void isp_mmu_flush_tlb_all(struct isp_mmu *mmu)
{
if (mmu->driver && mmu->driver->tlb_flush_all)
mmu->driver->tlb_flush_all(mmu);
}
Annotation
- Immediate include surface: `linux/types.h`, `linux/mutex.h`, `linux/slab.h`.
- Detected declarations: `struct isp_mmu`, `struct isp_mmu_client`, `struct isp_mmu`, `function isp_mmu_flush_tlb_all`, `function isp_mmu_flush_tlb_range`.
- Atlas domain: Driver Families / drivers/staging.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.