drivers/staging/media/atomisp/pci/atomisp-regs.h

Source file repositories/reference/linux-study-clean/drivers/staging/media/atomisp/pci/atomisp-regs.h

File Facts

System
Linux kernel
Corpus path
drivers/staging/media/atomisp/pci/atomisp-regs.h
Extension
.h
Size
6179 bytes
Lines
186
Domain
Driver Families
Bucket
drivers/staging
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef ATOMISP_REGS_H
#define ATOMISP_REGS_H

/* common register definitions */
#define PCICMDSTS		0x01
#define INTR			0x0f
#define MSI_CAPID		0x24
#define MSI_ADDRESS		0x25
#define MSI_DATA		0x26
#define INTR_CTL		0x27

#define PCI_MSI_CAPID		0x90
#define PCI_MSI_ADDR		0x94
#define PCI_MSI_DATA		0x98
#define PCI_INTERRUPT_CTRL	0x9C
#define PCI_I_CONTROL		0xfc

/* MRFLD specific register definitions */
#define MRFLD_CSI_AFE		0x39
#define MRFLD_CSI_CONTROL	0x3a
#define MRFLD_CSI_RCOMP		0x3d

#define MRFLD_PCI_PMCS		0x84
#define MRFLD_PCI_CSI_ACCESS_CTRL_VIOL	0xd4
#define MRFLD_PCI_CSI_AFE_HS_CONTROL	0xdc
#define MRFLD_PCI_CSI_AFE_RCOMP_CONTROL	0xe0
#define MRFLD_PCI_CSI_CONTROL		0xe8
#define MRFLD_PCI_CSI_AFE_TRIM_CONTROL	0xe4
#define MRFLD_PCI_CSI_DEADLINE_CONTROL	0xec
#define MRFLD_PCI_CSI_RCOMP_CONTROL	0xf4

/* Select Arasan (legacy)/Intel input system */
#define MRFLD_PCI_CSI_CONTROL_PARPATHEN	BIT(24)
/* Enable CSI interface (ANN B0/K0) */
#define MRFLD_PCI_CSI_CONTROL_CSI_READY	BIT(25)

/*
 * Enables the combining of adjacent 32-byte read requests to the same
 * cache line. When cleared, each 32-byte read request is sent as a
 * separate request on the IB interface.
 */
#define MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING	0x1

/*
 * Register: MRFLD_PCI_CSI_RCOMP_CONTROL
 * If cleared, the high speed clock going to the digital logic is gated when
 * RCOMP update is happening. The clock is gated for a minimum of 100 nsec.
 * If this bit is set, then the high speed clock is not gated during the
 * update cycle.
 */
#define MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE		0x800000

/*
 * Enables the combining of adjacent 32-byte write requests to the same
 * cache line. When cleared, each 32-byte write request is sent as a
 * separate request on the IB interface.
 */
#define MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING	0x2

#define MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK		0xc

#define MRFLD_PCI_CSI1_HSRXCLKTRIM		0x2
#define MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT	16
#define MRFLD_PCI_CSI2_HSRXCLKTRIM		0x3
#define MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT	24
#define MRFLD_PCI_CSI3_HSRXCLKTRIM		0x2
#define MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT	28
#define MRFLD_PCI_CSI_HSRXCLKTRIM_MASK		0xf

/*
 * This register is IUINT MMIO register, it is used to select the CSI
 * receiver backend.
 * 1: SH CSI backend
 * 0: Arasan CSI backend
 */
#define MRFLD_CSI_RECEIVER_SELECTION_REG       0x8081c

#define MRFLD_INTR_CLEAR_REG		       0x50c
#define MRFLD_INTR_STATUS_REG		       0x508
#define MRFLD_INTR_ENABLE_REG		       0x510

#define MRFLD_MAX_ZOOM_FACTOR	1024

/* MRFLD ISP POWER related */
#define MRFLD_ISPSSPM0         0x39
#define MRFLD_ISPSSPM0_ISPSSC_OFFSET   0
#define MRFLD_ISPSSPM0_ISPSSS_OFFSET   24
#define MRFLD_ISPSSPM0_ISPSSC_MASK     0x3
#define MRFLD_ISPSSPM0_IUNIT_POWER_ON  0
#define MRFLD_ISPSSPM0_IUNIT_POWER_OFF 0x3

Annotation

Implementation Notes