drivers/staging/media/atomisp/pci/css_2401_system/hrt/ibuf_cntrl_defs.h
Source file repositories/reference/linux-study-clean/drivers/staging/media/atomisp/pci/css_2401_system/hrt/ibuf_cntrl_defs.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/staging/media/atomisp/pci/css_2401_system/hrt/ibuf_cntrl_defs.h- Extension
.h- Size
- 5001 bytes
- Lines
- 127
- Domain
- Driver Families
- Bucket
- drivers/staging
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
stream2mmio_defs.hdma_v2_defs.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _ibuf_cntrl_defs_h_
#define _ibuf_cntrl_defs_h_
#include <stream2mmio_defs.h>
#include <dma_v2_defs.h>
#define _IBUF_CNTRL_REG_ALIGN 4
/* alignment of register banks, first bank are shared configuration and status registers: */
#define _IBUF_CNTRL_PROC_REG_ALIGN 32
/* the actual amount of configuration registers per proc: */
#define _IBUF_CNTRL_CONFIG_REGS_PER_PROC 18
/* the actual amount of shared configuration registers: */
#define _IBUF_CNTRL_CONFIG_REGS_NO_PROC 0
/* the actual amount of status registers per proc */
#define _IBUF_CNTRL_STATUS_REGS_PER_PROC (_IBUF_CNTRL_CONFIG_REGS_PER_PROC + 10)
/* the actual amount shared status registers */
#define _IBUF_CNTRL_STATUS_REGS_NO_PROC (_IBUF_CNTRL_CONFIG_REGS_NO_PROC + 2)
/* time out bits, maximum time out value is 2^_IBUF_CNTRL_TIME_OUT_BITS - 1 */
#define _IBUF_CNTRL_TIME_OUT_BITS 5
/* command token definition */
#define _IBUF_CNTRL_CMD_TOKEN_LSB 0
#define _IBUF_CNTRL_CMD_TOKEN_MSB 1
/* Str2MMIO defines */
#define _IBUF_CNTRL_STREAM2MMIO_CMD_TOKEN_MSB _STREAM2MMIO_CMD_TOKEN_CMD_MSB
#define _IBUF_CNTRL_STREAM2MMIO_CMD_TOKEN_LSB _STREAM2MMIO_CMD_TOKEN_CMD_LSB
#define _IBUF_CNTRL_STREAM2MMIO_NUM_ITEMS_BITS _STREAM2MMIO_PACK_NUM_ITEMS_BITS
#define _IBUF_CNTRL_STREAM2MMIO_ACK_EOF_BIT _STREAM2MMIO_PACK_ACK_EOF_BIT
#define _IBUF_CNTRL_STREAM2MMIO_ACK_TOKEN_VALID_BIT _STREAM2MMIO_ACK_TOKEN_VALID_BIT
/* acknowledge token definition */
#define _IBUF_CNTRL_ACK_TOKEN_STORES_IDX 0
#define _IBUF_CNTRL_ACK_TOKEN_STORES_BITS 15
#define _IBUF_CNTRL_ACK_TOKEN_ITEMS_IDX (_IBUF_CNTRL_ACK_TOKEN_STORES_BITS + _IBUF_CNTRL_ACK_TOKEN_STORES_IDX)
#define _IBUF_CNTRL_ACK_TOKEN_ITEMS_BITS _STREAM2MMIO_PACK_NUM_ITEMS_BITS
#define _IBUF_CNTRL_ACK_TOKEN_LSB _IBUF_CNTRL_ACK_TOKEN_STORES_IDX
#define _IBUF_CNTRL_ACK_TOKEN_MSB (_IBUF_CNTRL_ACK_TOKEN_ITEMS_BITS + _IBUF_CNTRL_ACK_TOKEN_ITEMS_IDX - 1)
/* bit 31 indicates a valid ack: */
#define _IBUF_CNTRL_ACK_TOKEN_VALID_BIT (_IBUF_CNTRL_ACK_TOKEN_ITEMS_BITS + _IBUF_CNTRL_ACK_TOKEN_ITEMS_IDX)
/*shared registers:*/
#define _IBUF_CNTRL_RECALC_WORDS_STATUS 0
#define _IBUF_CNTRL_ARBITERS_STATUS 1
#define _IBUF_CNTRL_SET_CRUN 2 /* NO PHYSICAL REGISTER!! Only used in HSS model */
/*register addresses for each proc: */
#define _IBUF_CNTRL_CMD 0
#define _IBUF_CNTRL_ACK 1
/* number of items (packets or words) per frame: */
#define _IBUF_CNTRL_NUM_ITEMS_PER_STORE 2
/* number of stores (packets or words) per store/buffer: */
#define _IBUF_CNTRL_NUM_STORES_PER_FRAME 3
/* the channel and command in the DMA */
#define _IBUF_CNTRL_DMA_CHANNEL 4
#define _IBUF_CNTRL_DMA_CMD 5
/* the start address and stride of the buffers */
#define _IBUF_CNTRL_BUFFER_START_ADDRESS 6
#define _IBUF_CNTRL_BUFFER_STRIDE 7
#define _IBUF_CNTRL_BUFFER_END_ADDRESS 8
/* destination start address, stride and end address; should be the same as in the DMA */
#define _IBUF_CNTRL_DEST_START_ADDRESS 9
#define _IBUF_CNTRL_DEST_STRIDE 10
#define _IBUF_CNTRL_DEST_END_ADDRESS 11
/* send a frame sync or not, default 1 */
#define _IBUF_CNTRL_SYNC_FRAME 12
/* str2mmio cmds */
#define _IBUF_CNTRL_STR2MMIO_SYNC_CMD 13
#define _IBUF_CNTRL_STR2MMIO_STORE_CMD 14
/* num elems p word*/
#define _IBUF_CNTRL_SHIFT_ITEMS 15
#define _IBUF_CNTRL_ELEMS_P_WORD_IBUF 16
#define _IBUF_CNTRL_ELEMS_P_WORD_DEST 17
/* STATUS */
/* current frame and stores in buffer */
#define _IBUF_CNTRL_CUR_STORES 18
#define _IBUF_CNTRL_CUR_ACKS 19
Annotation
- Immediate include surface: `stream2mmio_defs.h`, `dma_v2_defs.h`.
- Atlas domain: Driver Families / drivers/staging.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.