drivers/staging/media/atomisp/pci/css_2401_system/hrt/mipi_backend_defs.h

Source file repositories/reference/linux-study-clean/drivers/staging/media/atomisp/pci/css_2401_system/hrt/mipi_backend_defs.h

File Facts

System
Linux kernel
Corpus path
drivers/staging/media/atomisp/pci/css_2401_system/hrt/mipi_backend_defs.h
Extension
.h
Size
14385 bytes
Lines
201
Domain
Driver Families
Bucket
drivers/staging
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _mipi_backend_defs_h
#define _mipi_backend_defs_h

#include "mipi_backend_common_defs.h"

#define MIPI_BACKEND_REG_ALIGN                    4 // assuming 32 bit control bus width

#define _HRT_MIPI_BACKEND_NOF_IRQS                         3 // sid_lut

// SH Backend Register IDs
#define _HRT_MIPI_BACKEND_ENABLE_REG_IDX                   0
#define _HRT_MIPI_BACKEND_STATUS_REG_IDX                   1
//#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_IDX                2
#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX             2
#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG1_IDX             3
#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG2_IDX             4
#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG3_IDX             5
#define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_IDX             6
#define _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_IDX             7
#define _HRT_MIPI_BACKEND_FORCE_RAW8_REG_IDX               8
#define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_IDX               9
#define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_IDX               10
////
#define _HRT_MIPI_BACKEND_CUST_EN_REG_IDX                 11
#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX         12
#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX       13
#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P1_REG_IDX       14
#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P2_REG_IDX       15
#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P3_REG_IDX       16
#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P0_REG_IDX       17
#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P1_REG_IDX       18
#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P2_REG_IDX       19
#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P3_REG_IDX       20
#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P0_REG_IDX       21
#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P1_REG_IDX       22
#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P2_REG_IDX       23
#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P3_REG_IDX       24
#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_REG_IDX      25
////
#define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_IDX    26
#define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_IDX        27
//#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_IDX           28
#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX          28
#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_IDX          29
#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_IDX          30
#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_IDX          31

#define _HRT_MIPI_BACKEND_NOF_REGISTERS                   32 // excluding the LP LUT entries

#define _HRT_MIPI_BACKEND_LP_LUT_ENTRY_0_REG_IDX          32

/////////////////////////////////////////////////////////////////////////////////////////////////////
#define _HRT_MIPI_BACKEND_ENABLE_REG_WIDTH                 1
#define _HRT_MIPI_BACKEND_STATUS_REG_WIDTH                 1
//#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_WIDTH              1
#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG_WIDTH           32
#define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_WIDTH           7
#define _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_WIDTH           9
#define _HRT_MIPI_BACKEND_FORCE_RAW8_REG_WIDTH             8
#define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_WIDTH            _HRT_MIPI_BACKEND_NOF_IRQS
#define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_WIDTH              0
#define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_WIDTH   1
#define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_WIDTH       1 + 2 + 6
//#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_WIDTH          1
//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_WIDTH         7
//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_WIDTH         7
//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_WIDTH         7
//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_WIDTH         7

/////////////////////////////////////////////////////////////////////////////////////////////////////

#define _HRT_MIPI_BACKEND_NOF_SP_LUT_ENTRIES               4

//#define _HRT_MIPI_BACKEND_MAX_NOF_LP_LUT_ENTRIES           16  // to satisfy hss model static array declaration

#define _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH                 2
#define _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH                6
#define _HRT_MIPI_BACKEND_PACKET_ID_WIDTH                  _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH + _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH

#define _HRT_MIPI_BACKEND_STREAMING_PIX_A_LSB                 0
#define _HRT_MIPI_BACKEND_STREAMING_PIX_A_MSB(pix_width)     (_HRT_MIPI_BACKEND_STREAMING_PIX_A_LSB + (pix_width) - 1)
#define _HRT_MIPI_BACKEND_STREAMING_PIX_A_VAL_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_MSB(pix_width) + 1)
#define _HRT_MIPI_BACKEND_STREAMING_PIX_B_LSB(pix_width)     (_HRT_MIPI_BACKEND_STREAMING_PIX_A_VAL_BIT(pix_width) + 1)
#define _HRT_MIPI_BACKEND_STREAMING_PIX_B_MSB(pix_width)     (_HRT_MIPI_BACKEND_STREAMING_PIX_B_LSB(pix_width) + (pix_width) - 1)
#define _HRT_MIPI_BACKEND_STREAMING_PIX_B_VAL_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_MSB(pix_width) + 1)
#define _HRT_MIPI_BACKEND_STREAMING_SOP_BIT(pix_width)       (_HRT_MIPI_BACKEND_STREAMING_PIX_B_VAL_BIT(pix_width) + 1)
#define _HRT_MIPI_BACKEND_STREAMING_EOP_BIT(pix_width)       (_HRT_MIPI_BACKEND_STREAMING_SOP_BIT(pix_width) + 1)
#define _HRT_MIPI_BACKEND_STREAMING_WIDTH(pix_width)         (_HRT_MIPI_BACKEND_STREAMING_EOP_BIT(pix_width) + 1)

/*************************************************************************************************/

Annotation

Implementation Notes