drivers/staging/media/atomisp/pci/hive_isp_css_defs.h

Source file repositories/reference/linux-study-clean/drivers/staging/media/atomisp/pci/hive_isp_css_defs.h

File Facts

System
Linux kernel
Corpus path
drivers/staging/media/atomisp/pci/hive_isp_css_defs.h
Extension
.h
Size
22068 bytes
Lines
404
Domain
Driver Families
Bucket
drivers/staging
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _hive_isp_css_defs_h__
#define _hive_isp_css_defs_h__

#define HIVE_ISP_CTRL_DATA_WIDTH     32
#define HIVE_ISP_CTRL_ADDRESS_WIDTH  32
#define HIVE_ISP_CTRL_MAX_BURST_SIZE  1
#define HIVE_ISP_DDR_ADDRESS_WIDTH   36

#define HIVE_ISP_HOST_MAX_BURST_SIZE  8 /* host supports bursts in order to prevent repeating DDRAM accesses */
#define HIVE_ISP_NUM_GPIO_PINS       12

/* This list of vector num_elems/elem_bits pairs is valid both in C as initializer
   and in the DMA parameter list */
#define HIVE_ISP_DDR_DMA_SPECS {{32,  8}, {16, 16}, {18, 14}, {25, 10}, {21, 12}}
#define HIVE_ISP_DDR_WORD_BITS 256
#define HIVE_ISP_DDR_WORD_BYTES  (HIVE_ISP_DDR_WORD_BITS / 8)
#define HIVE_ISP_DDR_BYTES       (512 * 1024 * 1024) /* hss only */
#define HIVE_ISP_DDR_BYTES_RTL   (127 * 1024 * 1024) /* RTL only */
#define HIVE_ISP_DDR_SMALL_BYTES (128 * 256 / 8)
#define HIVE_ISP_PAGE_SHIFT    12
#define HIVE_ISP_PAGE_SIZE     BIT(HIVE_ISP_PAGE_SHIFT)

#define CSS_DDR_WORD_BITS        HIVE_ISP_DDR_WORD_BITS
#define CSS_DDR_WORD_BYTES       HIVE_ISP_DDR_WORD_BYTES

/* If HIVE_ISP_DDR_BASE_OFFSET is set to a non-zero value, the wide bus just before the DDRAM gets an extra dummy port where         */
/* address range 0 .. HIVE_ISP_DDR_BASE_OFFSET-1 maps onto. This effectively creates an offset for the DDRAM from system perspective */
#define HIVE_ISP_DDR_BASE_OFFSET 0x120000000 /* 0x200000 */

#define HIVE_DMA_ISP_BUS_CONN 0
#define HIVE_DMA_ISP_DDR_CONN 1
#define HIVE_DMA_BUS_DDR_CONN 2
#define HIVE_DMA_ISP_MASTER master_port0
#define HIVE_DMA_BUS_MASTER master_port1
#define HIVE_DMA_DDR_MASTER master_port2

#define HIVE_DMA_NUM_CHANNELS       32 /* old value was  8 */
#define HIVE_DMA_CMD_FIFO_DEPTH     24 /* old value was 12 */

#define HIVE_IF_PIXEL_WIDTH 12

#define HIVE_MMU_TLB_SETS           8
#define HIVE_MMU_TLB_SET_BLOCKS     8
#define HIVE_MMU_TLB_BLOCK_ELEMENTS 8
#define HIVE_MMU_PAGE_TABLE_LEVELS  2
#define HIVE_MMU_PAGE_BYTES         HIVE_ISP_PAGE_SIZE

#define HIVE_ISP_CH_ID_BITS    2
#define HIVE_ISP_FMT_TYPE_BITS 5
#define HIVE_ISP_ISEL_SEL_BITS 2

#define HIVE_GP_REGS_SDRAM_WAKEUP_IDX                           0
#define HIVE_GP_REGS_IDLE_IDX                                   1
#define HIVE_GP_REGS_IRQ_0_IDX                                  2
#define HIVE_GP_REGS_IRQ_1_IDX                                  3
#define HIVE_GP_REGS_SP_STREAM_STAT_IDX                         4
#define HIVE_GP_REGS_SP_STREAM_STAT_B_IDX                       5
#define HIVE_GP_REGS_ISP_STREAM_STAT_IDX                        6
#define HIVE_GP_REGS_MOD_STREAM_STAT_IDX                        7
#define HIVE_GP_REGS_SP_STREAM_STAT_IRQ_COND_IDX                8
#define HIVE_GP_REGS_SP_STREAM_STAT_B_IRQ_COND_IDX              9
#define HIVE_GP_REGS_ISP_STREAM_STAT_IRQ_COND_IDX              10
#define HIVE_GP_REGS_MOD_STREAM_STAT_IRQ_COND_IDX              11
#define HIVE_GP_REGS_SP_STREAM_STAT_IRQ_ENABLE_IDX             12
#define HIVE_GP_REGS_SP_STREAM_STAT_B_IRQ_ENABLE_IDX           13
#define HIVE_GP_REGS_ISP_STREAM_STAT_IRQ_ENABLE_IDX            14
#define HIVE_GP_REGS_MOD_STREAM_STAT_IRQ_ENABLE_IDX            15
#define HIVE_GP_REGS_SWITCH_PRIM_IF_IDX                        16
#define HIVE_GP_REGS_SWITCH_GDC1_IDX                           17
#define HIVE_GP_REGS_SWITCH_GDC2_IDX                           18
#define HIVE_GP_REGS_SRST_IDX                                  19
#define HIVE_GP_REGS_SLV_REG_SRST_IDX                          20

/* Bit numbers of the soft reset register */
#define HIVE_GP_REGS_SRST_ISYS_CBUS                             0
#define HIVE_GP_REGS_SRST_ISEL_CBUS                             1
#define HIVE_GP_REGS_SRST_IFMT_CBUS                             2
#define HIVE_GP_REGS_SRST_GPDEV_CBUS                            3
#define HIVE_GP_REGS_SRST_GPIO                                  4
#define HIVE_GP_REGS_SRST_TC                                    5
#define HIVE_GP_REGS_SRST_GPTIMER                               6
#define HIVE_GP_REGS_SRST_FACELLFIFOS                           7
#define HIVE_GP_REGS_SRST_D_OSYS                                8
#define HIVE_GP_REGS_SRST_IFT_SEC_PIPE                          9
#define HIVE_GP_REGS_SRST_GDC1                                 10
#define HIVE_GP_REGS_SRST_GDC2                                 11
#define HIVE_GP_REGS_SRST_VEC_BUS                              12
#define HIVE_GP_REGS_SRST_ISP                                  13
#define HIVE_GP_REGS_SRST_SLV_GRP_BUS                          14
#define HIVE_GP_REGS_SRST_DMA                                  15

Annotation

Implementation Notes