drivers/staging/media/atomisp/pci/input_system_ctrl_defs.h

Source file repositories/reference/linux-study-clean/drivers/staging/media/atomisp/pci/input_system_ctrl_defs.h

File Facts

System
Linux kernel
Corpus path
drivers/staging/media/atomisp/pci/input_system_ctrl_defs.h
Extension
.h
Size
9979 bytes
Lines
236
Domain
Driver Families
Bucket
drivers/staging
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _input_system_ctrl_defs_h
#define _input_system_ctrl_defs_h

#define _INPUT_SYSTEM_CTRL_REG_ALIGN                    4  /* assuming 32 bit control bus width */

/* --------------------------------------------------*/

/* --------------------------------------------------*/
/* REGISTER INFO */
/* --------------------------------------------------*/

// Number of registers
#define ISYS_CTRL_NOF_REGS                              23

// Register id's of MMIO slave accessible registers
#define ISYS_CTRL_CAPT_START_ADDR_A_REG_ID              0
#define ISYS_CTRL_CAPT_START_ADDR_B_REG_ID              1
#define ISYS_CTRL_CAPT_START_ADDR_C_REG_ID              2
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID         3
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID         4
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID         5
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID         6
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID         7
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID         8
#define ISYS_CTRL_ACQ_START_ADDR_REG_ID                 9
#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID            10
#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID            11
#define ISYS_CTRL_INIT_REG_ID                           12
#define ISYS_CTRL_LAST_COMMAND_REG_ID                   13
#define ISYS_CTRL_NEXT_COMMAND_REG_ID                   14
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_ID               15
#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_ID               16
#define ISYS_CTRL_FSM_STATE_INFO_REG_ID                 17
#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_ID          18
#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_ID          19
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID          20
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID             21
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID    22

/* register reset value */
#define ISYS_CTRL_CAPT_START_ADDR_A_REG_RSTVAL           0
#define ISYS_CTRL_CAPT_START_ADDR_B_REG_RSTVAL           0
#define ISYS_CTRL_CAPT_START_ADDR_C_REG_RSTVAL           0
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_RSTVAL      128
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_RSTVAL      128
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_RSTVAL      128
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL      3
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL      3
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL      3
#define ISYS_CTRL_ACQ_START_ADDR_REG_RSTVAL              0
#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL         128
#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL         3
#define ISYS_CTRL_INIT_REG_RSTVAL                        0
#define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL                15    //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_NEXT_COMMAND_REG_RSTVAL                15    //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_RSTVAL            15    //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_RSTVAL            15    //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
#define ISYS_CTRL_FSM_STATE_INFO_REG_RSTVAL              0
#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL       0
#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_RSTVAL       0
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_RSTVAL       0
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_RSTVAL          0
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_RSTVAL 0

/* register width value */
#define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH            9
#define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH            9
#define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH            9
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH       9
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH       9
#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH       9
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH       9
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH       9
#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH       9
#define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH               9
#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH          9
#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH          9
#define ISYS_CTRL_INIT_REG_WIDTH                         3
#define ISYS_CTRL_LAST_COMMAND_REG_WIDTH                 32    /* slave data width */
#define ISYS_CTRL_NEXT_COMMAND_REG_WIDTH                 32
#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_WIDTH             32
#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_WIDTH             32
#define ISYS_CTRL_FSM_STATE_INFO_REG_WIDTH               32
#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_WIDTH        32
#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_WIDTH        32
#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_WIDTH        32
#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_WIDTH           32
#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_WIDTH  1

/* bit definitions */

Annotation

Implementation Notes