drivers/staging/media/atomisp/pci/isp_acquisition_defs.h

Source file repositories/reference/linux-study-clean/drivers/staging/media/atomisp/pci/isp_acquisition_defs.h

File Facts

System
Linux kernel
Corpus path
drivers/staging/media/atomisp/pci/isp_acquisition_defs.h
Extension
.h
Size
12180 bytes
Lines
222
Domain
Driver Families
Bucket
drivers/staging
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _isp_acquisition_defs_h
#define _isp_acquisition_defs_h

#define _ISP_ACQUISITION_REG_ALIGN                4  /* assuming 32 bit control bus width */
#define _ISP_ACQUISITION_BYTES_PER_ELEM           4

/* --------------------------------------------------*/

#define NOF_ACQ_IRQS                              1

/* --------------------------------------------------*/
/* FSM */
/* --------------------------------------------------*/
#define MEM2STREAM_FSM_STATE_BITS                 2
#define ACQ_SYNCHRONIZER_FSM_STATE_BITS           2

/* --------------------------------------------------*/
/* REGISTER INFO */
/* --------------------------------------------------*/

#define NOF_ACQ_REGS                              12

// Register id's of MMIO slave accessible registers
#define ACQ_START_ADDR_REG_ID                     0
#define ACQ_MEM_REGION_SIZE_REG_ID                1
#define ACQ_NUM_MEM_REGIONS_REG_ID                2
#define ACQ_INIT_REG_ID                           3
#define ACQ_RECEIVED_SHORT_PACKETS_REG_ID         4
#define ACQ_RECEIVED_LONG_PACKETS_REG_ID          5
#define ACQ_LAST_COMMAND_REG_ID                   6
#define ACQ_NEXT_COMMAND_REG_ID                   7
#define ACQ_LAST_ACKNOWLEDGE_REG_ID               8
#define ACQ_NEXT_ACKNOWLEDGE_REG_ID               9
#define ACQ_FSM_STATE_INFO_REG_ID                 10
#define ACQ_INT_CNTR_INFO_REG_ID                  11

// Register width
#define ACQ_START_ADDR_REG_WIDTH                  9
#define ACQ_MEM_REGION_SIZE_REG_WIDTH             9
#define ACQ_NUM_MEM_REGIONS_REG_WIDTH             9
#define ACQ_INIT_REG_WIDTH                        3
#define ACQ_RECEIVED_SHORT_PACKETS_REG_WIDTH      32
#define ACQ_RECEIVED_LONG_PACKETS_REG_WIDTH       32
#define ACQ_LAST_COMMAND_REG_WIDTH                32
#define ACQ_NEXT_COMMAND_REG_WIDTH                32
#define ACQ_LAST_ACKNOWLEDGE_REG_WIDTH            32
#define ACQ_NEXT_ACKNOWLEDGE_REG_WIDTH            32
#define ACQ_FSM_STATE_INFO_REG_WIDTH              ((MEM2STREAM_FSM_STATE_BITS * 3) + (ACQ_SYNCHRONIZER_FSM_STATE_BITS * 3))
#define ACQ_INT_CNTR_INFO_REG_WIDTH               32

/* register reset value */
#define ACQ_START_ADDR_REG_RSTVAL                 0
#define ACQ_MEM_REGION_SIZE_REG_RSTVAL            128
#define ACQ_NUM_MEM_REGIONS_REG_RSTVAL            3
#define ACQ_INIT_REG_RSTVAL                       0
#define ACQ_RECEIVED_SHORT_PACKETS_REG_RSTVAL     0
#define ACQ_RECEIVED_LONG_PACKETS_REG_RSTVAL      0
#define ACQ_LAST_COMMAND_REG_RSTVAL               0
#define ACQ_NEXT_COMMAND_REG_RSTVAL               0
#define ACQ_LAST_ACKNOWLEDGE_REG_RSTVAL           0
#define ACQ_NEXT_ACKNOWLEDGE_REG_RSTVAL           0
#define ACQ_FSM_STATE_INFO_REG_RSTVAL             0
#define ACQ_INT_CNTR_INFO_REG_RSTVAL              0

/* bit definitions */
#define ACQ_INIT_RST_REG_BIT                      0
#define ACQ_INIT_RESYNC_BIT                       2
#define ACQ_INIT_RST_IDX                          ACQ_INIT_RST_REG_BIT
#define ACQ_INIT_RST_BITS                         1
#define ACQ_INIT_RESYNC_IDX                       ACQ_INIT_RESYNC_BIT
#define ACQ_INIT_RESYNC_BITS                      1

/* --------------------------------------------------*/
/* TOKEN INFO */
/* --------------------------------------------------*/
#define ACQ_TOKEN_ID_LSB                          0
#define ACQ_TOKEN_ID_MSB                          3
#define ACQ_TOKEN_WIDTH                           (ACQ_TOKEN_ID_MSB - ACQ_TOKEN_ID_LSB  + 1) // 4
#define ACQ_TOKEN_ID_IDX                          0
#define ACQ_TOKEN_ID_BITS                         ACQ_TOKEN_WIDTH
#define ACQ_INIT_CMD_INIT_IDX                     4
#define ACQ_INIT_CMD_INIT_BITS                    3
#define ACQ_CMD_START_ADDR_IDX                    4
#define ACQ_CMD_START_ADDR_BITS                   9
#define ACQ_CMD_NOFWORDS_IDX                      13
#define ACQ_CMD_NOFWORDS_BITS                     9
#define ACQ_MEM_REGION_ID_IDX                     22
#define ACQ_MEM_REGION_ID_BITS                    9
#define ACQ_PACKET_LENGTH_TOKEN_MSB               21
#define ACQ_PACKET_LENGTH_TOKEN_LSB               13

Annotation

Implementation Notes