drivers/staging/media/atomisp/pci/isp_capture_defs.h

Source file repositories/reference/linux-study-clean/drivers/staging/media/atomisp/pci/isp_capture_defs.h

File Facts

System
Linux kernel
Corpus path
drivers/staging/media/atomisp/pci/isp_capture_defs.h
Extension
.h
Size
15281 bytes
Lines
271
Domain
Driver Families
Bucket
drivers/staging
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _isp_capture_defs_h
#define _isp_capture_defs_h

#define _ISP_CAPTURE_REG_ALIGN                    4  /* assuming 32 bit control bus width */
#define _ISP_CAPTURE_BITS_PER_ELEM                32  /* only for data, not SOP */
#define _ISP_CAPTURE_BYTES_PER_ELEM               (_ISP_CAPTURE_BITS_PER_ELEM / 8)
#define _ISP_CAPTURE_BYTES_PER_WORD               32		/* 256/8 */
#define _ISP_CAPTURE_ELEM_PER_WORD                _ISP_CAPTURE_BYTES_PER_WORD / _ISP_CAPTURE_BYTES_PER_ELEM

/* --------------------------------------------------*/

#define NOF_IRQS                                  2

/* --------------------------------------------------*/
/* REGISTER INFO */
/* --------------------------------------------------*/

// Number of registers
#define CAPT_NOF_REGS                             16

// Register id's of MMIO slave accessible registers
#define CAPT_START_MODE_REG_ID                    0
#define CAPT_START_ADDR_REG_ID                    1
#define CAPT_MEM_REGION_SIZE_REG_ID               2
#define CAPT_NUM_MEM_REGIONS_REG_ID               3
#define CAPT_INIT_REG_ID                          4
#define CAPT_START_REG_ID                         5
#define CAPT_STOP_REG_ID                          6

#define CAPT_PACKET_LENGTH_REG_ID                 7
#define CAPT_RECEIVED_LENGTH_REG_ID               8
#define CAPT_RECEIVED_SHORT_PACKETS_REG_ID        9
#define CAPT_RECEIVED_LONG_PACKETS_REG_ID         10
#define CAPT_LAST_COMMAND_REG_ID                  11
#define CAPT_NEXT_COMMAND_REG_ID                  12
#define CAPT_LAST_ACKNOWLEDGE_REG_ID              13
#define CAPT_NEXT_ACKNOWLEDGE_REG_ID              14
#define CAPT_FSM_STATE_INFO_REG_ID                15

// Register width
#define CAPT_START_MODE_REG_WIDTH                 1

#define CAPT_START_REG_WIDTH                      1
#define CAPT_STOP_REG_WIDTH                       1

/* --------------------------------------------------*/
/* FSM */
/* --------------------------------------------------*/
#define CAPT_WRITE2MEM_FSM_STATE_BITS             2
#define CAPT_SYNCHRONIZER_FSM_STATE_BITS          3

#define CAPT_PACKET_LENGTH_REG_WIDTH              17
#define CAPT_RECEIVED_LENGTH_REG_WIDTH            17
#define CAPT_RECEIVED_SHORT_PACKETS_REG_WIDTH     32
#define CAPT_RECEIVED_LONG_PACKETS_REG_WIDTH      32
#define CAPT_LAST_COMMAND_REG_WIDTH               32
#define CAPT_LAST_ACKNOWLEDGE_REG_WIDTH           32
#define CAPT_NEXT_ACKNOWLEDGE_REG_WIDTH           32
#define CAPT_FSM_STATE_INFO_REG_WIDTH             ((CAPT_WRITE2MEM_FSM_STATE_BITS * 3) + (CAPT_SYNCHRONIZER_FSM_STATE_BITS * 3))

/* register reset value */
#define CAPT_START_MODE_REG_RSTVAL                0
#define CAPT_START_ADDR_REG_RSTVAL                0
#define CAPT_MEM_REGION_SIZE_REG_RSTVAL           128
#define CAPT_NUM_MEM_REGIONS_REG_RSTVAL           3
#define CAPT_INIT_REG_RSTVAL                      0

#define CAPT_START_REG_RSTVAL                     0
#define CAPT_STOP_REG_RSTVAL                      0

#define CAPT_PACKET_LENGTH_REG_RSTVAL             0
#define CAPT_RECEIVED_LENGTH_REG_RSTVAL           0
#define CAPT_RECEIVED_SHORT_PACKETS_REG_RSTVAL    0
#define CAPT_RECEIVED_LONG_PACKETS_REG_RSTVAL     0
#define CAPT_LAST_COMMAND_REG_RSTVAL              0
#define CAPT_NEXT_COMMAND_REG_RSTVAL              0
#define CAPT_LAST_ACKNOWLEDGE_REG_RSTVAL          0
#define CAPT_NEXT_ACKNOWLEDGE_REG_RSTVAL          0
#define CAPT_FSM_STATE_INFO_REG_RSTVAL            0

/* bit definitions */
#define CAPT_INIT_RST_REG_BIT                     0
#define CAPT_INIT_FLUSH_BIT                       1
#define CAPT_INIT_RESYNC_BIT                      2
#define CAPT_INIT_RESTART_BIT                     3
#define CAPT_INIT_RESTART_MEM_ADDR_LSB            4

#define CAPT_INIT_RST_REG_IDX                     CAPT_INIT_RST_REG_BIT
#define CAPT_INIT_RST_REG_BITS                    1
#define CAPT_INIT_FLUSH_IDX                       CAPT_INIT_FLUSH_BIT

Annotation

Implementation Notes