drivers/staging/media/atomisp/pci/runtime/queue/interface/ia_css_queue_comm.h

File Facts

System

Linux kernel

Corpus path

drivers/staging/media/atomisp/pci/runtime/queue/interface/ia_css_queue_comm.h

Extension

.h

Size

1448 bytes

Lines

46

Domain

Driver Families

Bucket

drivers/staging

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• type_support.h
• ia_css_circbuf.h

Detected Declarations

• struct ia_css_queue_remote

Annotated Snippet

struct ia_css_queue_remote {
	u32 cb_desc_addr; /*Circbuf desc address for remote queues*/
	u32 cb_elems_addr; /*Circbuf elements addr for remote queue*/
	u8 location;    /* Cell location for queue */
	u8 proc_id;     /* Processor id for queue access */
};

typedef struct ia_css_queue_remote ia_css_queue_remote_t;

#endif /* __IA_CSS_QUEUE_COMM_H */

Annotation

• Immediate include surface: `type_support.h`, `ia_css_circbuf.h`.
• Detected declarations: `struct ia_css_queue_remote`.
• Atlas domain: Driver Families / drivers/staging.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.