drivers/staging/media/imx/imx6-mipi-csi2.c

Source file repositories/reference/linux-study-clean/drivers/staging/media/imx/imx6-mipi-csi2.c

File Facts

System
Linux kernel
Corpus path
drivers/staging/media/imx/imx6-mipi-csi2.c
Extension
.c
Size
21269 bytes
Lines
839
Domain
Driver Families
Bucket
drivers/staging
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct csi2_dev {
	struct device *dev;
	struct v4l2_subdev sd;
	struct v4l2_async_notifier notifier;
	struct media_pad pad[CSI2_NUM_PADS];
	struct clk *dphy_clk;
	struct clk *pllref_clk;
	struct clk *pix_clk; /* what is this? */
	void __iomem *base;

	struct v4l2_subdev *remote;
	unsigned int remote_pad;
	unsigned short data_lanes;

	/* lock to protect all members below */
	struct mutex lock;

	struct v4l2_mbus_framefmt format_mbus;

	int stream_count;
	struct v4l2_subdev *src_sd;
	bool sink_linked[CSI2_NUM_SRC_PADS];
};

#define DEVICE_NAME "imx6-mipi-csi2"

/* Register offsets */
#define CSI2_VERSION		0x000
#define CSI2_N_LANES		0x004
#define CSI2_PHY_SHUTDOWNZ	0x008
#define CSI2_DPHY_RSTZ		0x00c
#define CSI2_RESETN		0x010
#define CSI2_PHY_STATE		0x014
#define PHY_STOPSTATEDATA_BIT	4
#define PHY_STOPSTATEDATA(n)	BIT(PHY_STOPSTATEDATA_BIT + (n))
#define PHY_RXCLKACTIVEHS	BIT(8)
#define PHY_RXULPSCLKNOT	BIT(9)
#define PHY_STOPSTATECLK	BIT(10)
#define CSI2_DATA_IDS_1		0x018
#define CSI2_DATA_IDS_2		0x01c
#define CSI2_ERR1		0x020
#define CSI2_ERR2		0x024
#define CSI2_MSK1		0x028
#define CSI2_MSK2		0x02c
#define CSI2_PHY_TST_CTRL0	0x030
#define PHY_TESTCLR		BIT(0)
#define PHY_TESTCLK		BIT(1)
#define CSI2_PHY_TST_CTRL1	0x034
#define PHY_TESTEN		BIT(16)
/*
 * i.MX CSI2IPU Gasket registers follow. The CSI2IPU gasket is
 * not part of the MIPI CSI-2 core, but its registers fall in the
 * same register map range.
 */
#define CSI2IPU_GASKET		0xf00
#define CSI2IPU_YUV422_YUYV	BIT(2)

static inline struct csi2_dev *sd_to_dev(struct v4l2_subdev *sdev)
{
	return container_of(sdev, struct csi2_dev, sd);
}

static inline struct csi2_dev *notifier_to_dev(struct v4l2_async_notifier *n)
{
	return container_of(n, struct csi2_dev, notifier);
}

/*
 * The required sequence of MIPI CSI-2 startup as specified in the i.MX6
 * reference manual is as follows:
 *
 * 1. Deassert presetn signal (global reset).
 *	It's not clear what this "global reset" signal is (maybe APB
 *	global reset), but in any case this step would be probably
 *	be carried out during driver load in csi2_probe().
 *
 * 2. Configure MIPI Camera Sensor to put all Tx lanes in LP-11 state.
 *	This must be carried out by the MIPI sensor's s_power(ON) subdev
 *	op.
 *
 * 3. D-PHY initialization.
 * 4. CSI2 Controller programming (Set N_LANES, deassert PHY_SHUTDOWNZ,
 *    deassert PHY_RSTZ, deassert CSI2_RESETN).
 * 5. Read the PHY status register (PHY_STATE) to confirm that all data and
 *    clock lanes of the D-PHY are in LP-11 state.
 * 6. Configure the MIPI Camera Sensor to start transmitting a clock on the
 *    D-PHY clock lane.
 * 7. CSI2 Controller programming - Read the PHY status register (PHY_STATE)
 *    to confirm that the D-PHY is receiving a clock on the D-PHY clock lane.
 *

Annotation

Implementation Notes