drivers/staging/media/ipu7/ipu7-buttress.c
Source file repositories/reference/linux-study-clean/drivers/staging/media/ipu7/ipu7-buttress.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/staging/media/ipu7/ipu7-buttress.c- Extension
.c- Size
- 32944 bytes
- Lines
- 1208
- Domain
- Driver Families
- Bucket
- drivers/staging
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
asm/cpu_device_id.hlinux/bitfield.hlinux/bits.hlinux/completion.hlinux/device.hlinux/dma-mapping.hlinux/firmware.hlinux/interrupt.hlinux/iopoll.hlinux/math64.hlinux/mm.hlinux/mutex.hlinux/module.hlinux/pci.hlinux/pm_runtime.hlinux/scatterlist.hlinux/types.hipu7.hipu7-bus.hipu7-buttress.hipu7-buttress-regs.h
Detected Declarations
struct ipu7_ipc_buttress_msgfunction ipu_buttress_ipc_resetfunction ipu_buttress_ipc_validity_closefunction ipu_buttress_ipc_validity_openfunction ipu_buttress_ipc_recvfunction ipu_buttress_ipc_send_msgfunction ipu_buttress_ipc_sendfunction ipu_buttress_call_isrfunction ipu_buttress_isrfunction ipu_buttress_isr_threadedfunction isys_d2d_powerfunction isys_nde_controlfunction ipu7_buttress_powerupfunction ipu7_buttress_powerdownfunction ipu8_buttress_powerupfunction ipu8_buttress_powerdownfunction ipu_buttress_powerupfunction ipu_buttress_powerdownfunction ipu_buttress_get_secure_modefunction ipu_buttress_auth_donefunction ipu_buttress_get_isys_freqfunction ipu_buttress_get_psys_freqfunction ipu_buttress_reset_authenticationfunction ipu_buttress_authenticatefunction ipu_buttress_send_tsc_requestfunction ipu_buttress_start_tsc_syncfunction ipu_buttress_tsc_readfunction ipu_buttress_tsc_ticks_to_nsfunction ipu_buttress_wakeup_is_ucfunction ipu_buttress_wakeup_ps_ucfunction ipu_buttress_setupfunction ipu_buttress_restorefunction ipu_buttress_initfunction ipu_buttress_exit
Annotated Snippet
struct ipu7_ipc_buttress_msg {
u32 cmd;
u32 expected_resp;
bool require_resp;
u8 cmd_size;
};
static const u32 ipu7_adev_irq_mask[2] = {
BUTTRESS_IRQ_IS_IRQ,
BUTTRESS_IRQ_PS_IRQ
};
int ipu_buttress_ipc_reset(struct ipu7_device *isp,
struct ipu_buttress_ipc *ipc)
{
unsigned int retries = BUTTRESS_IPC_RESET_RETRY;
struct ipu_buttress *b = &isp->buttress;
struct device *dev = &isp->pdev->dev;
u32 val = 0, csr_in_clr;
if (!isp->secure_mode) {
dev_dbg(dev, "Skip IPC reset for non-secure mode\n");
return 0;
}
mutex_lock(&b->ipc_mutex);
/* Clear-by-1 CSR (all bits), corresponding internal states. */
val = readl(isp->base + ipc->csr_in);
writel(val, isp->base + ipc->csr_in);
/* Set peer CSR bit IPC_PEER_COMP_ACTIONS_RST_PHASE1 */
writel(ENTRY, isp->base + ipc->csr_out);
/*
* Clear-by-1 all CSR bits EXCEPT following
* bits:
* A. IPC_PEER_COMP_ACTIONS_RST_PHASE1.
* B. IPC_PEER_COMP_ACTIONS_RST_PHASE2.
* C. Possibly custom bits, depending on
* their role.
*/
csr_in_clr = BUTTRESS_IU2CSECSR_IPC_PEER_DEASSERTED_REG_VALID_REQ |
BUTTRESS_IU2CSECSR_IPC_PEER_ACKED_REG_VALID |
BUTTRESS_IU2CSECSR_IPC_PEER_ASSERTED_REG_VALID_REQ | QUERY;
do {
usleep_range(400, 500);
val = readl(isp->base + ipc->csr_in);
switch (val) {
case ENTRY | EXIT:
case ENTRY | EXIT | QUERY:
/*
* 1) Clear-by-1 CSR bits
* (IPC_PEER_COMP_ACTIONS_RST_PHASE1,
* IPC_PEER_COMP_ACTIONS_RST_PHASE2).
* 2) Set peer CSR bit
* IPC_PEER_QUERIED_IP_COMP_ACTIONS_RST_PHASE.
*/
writel(ENTRY | EXIT, isp->base + ipc->csr_in);
writel(QUERY, isp->base + ipc->csr_out);
break;
case ENTRY:
case ENTRY | QUERY:
/*
* 1) Clear-by-1 CSR bits
* (IPC_PEER_COMP_ACTIONS_RST_PHASE1,
* IPC_PEER_QUERIED_IP_COMP_ACTIONS_RST_PHASE).
* 2) Set peer CSR bit
* IPC_PEER_COMP_ACTIONS_RST_PHASE1.
*/
writel(ENTRY | QUERY, isp->base + ipc->csr_in);
writel(ENTRY, isp->base + ipc->csr_out);
break;
case EXIT:
case EXIT | QUERY:
/*
* Clear-by-1 CSR bit
* IPC_PEER_COMP_ACTIONS_RST_PHASE2.
* 1) Clear incoming doorbell.
* 2) Clear-by-1 all CSR bits EXCEPT following
* bits:
* A. IPC_PEER_COMP_ACTIONS_RST_PHASE1.
* B. IPC_PEER_COMP_ACTIONS_RST_PHASE2.
* C. Possibly custom bits, depending on
* their role.
* 3) Set peer CSR bit
* IPC_PEER_COMP_ACTIONS_RST_PHASE2.
*/
writel(EXIT, isp->base + ipc->csr_in);
writel(0, isp->base + ipc->db0_in);
Annotation
- Immediate include surface: `asm/cpu_device_id.h`, `linux/bitfield.h`, `linux/bits.h`, `linux/completion.h`, `linux/device.h`, `linux/dma-mapping.h`, `linux/firmware.h`, `linux/interrupt.h`.
- Detected declarations: `struct ipu7_ipc_buttress_msg`, `function ipu_buttress_ipc_reset`, `function ipu_buttress_ipc_validity_close`, `function ipu_buttress_ipc_validity_open`, `function ipu_buttress_ipc_recv`, `function ipu_buttress_ipc_send_msg`, `function ipu_buttress_ipc_send`, `function ipu_buttress_call_isr`, `function ipu_buttress_isr`, `function ipu_buttress_isr_threaded`.
- Atlas domain: Driver Families / drivers/staging.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.