drivers/staging/media/ipu7/ipu7.h

Source file repositories/reference/linux-study-clean/drivers/staging/media/ipu7/ipu7.h

File Facts

System
Linux kernel
Corpus path
drivers/staging/media/ipu7/ipu7.h
Extension
.h
Size
6189 bytes
Lines
243
Domain
Driver Families
Bucket
drivers/staging
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ipu7_device {
	struct pci_dev *pdev;
	struct list_head devices;
	struct ipu7_bus_device *isys;
	struct ipu7_bus_device *psys;
	struct ipu_buttress buttress;

	const struct firmware *cpd_fw;
	const char *cpd_fw_name;
	/* Only for non-secure mode. */
	void *fw_code_region;

	void __iomem *base;
	void __iomem *pb_base;
	u8 hw_ver;
	bool ipc_reinit;
	bool secure_mode;
	bool ipu7_bus_ready_to_probe;
};

#define IPU_DMA_MASK			39
#define IPU_LIB_CALL_TIMEOUT_MS		2000
#define IPU_PSYS_CMD_TIMEOUT_MS		2000
#define IPU_PSYS_OPEN_CLOSE_TIMEOUT_US	50
#define IPU_PSYS_OPEN_CLOSE_RETRY	(10000 / IPU_PSYS_OPEN_CLOSE_TIMEOUT_US)

#define IPU_ISYS_NAME "isys"
#define IPU_PSYS_NAME "psys"

#define IPU_MMU_ADDR_BITS		32
/* FW is accessible within the first 2 GiB only in non-secure mode. */
#define IPU_MMU_ADDR_BITS_NON_SECURE	31

#define IPU7_IS_MMU_NUM			4U
#define IPU7_PS_MMU_NUM			4U
#define IPU7P5_IS_MMU_NUM		4U
#define IPU7P5_PS_MMU_NUM		4U
#define IPU8_IS_MMU_NUM			5U
#define IPU8_PS_MMU_NUM			4U
#define IPU_MMU_MAX_NUM			5U /* max(IS, PS) */
#define IPU_MMU_MAX_TLB_L1_STREAMS	40U
#define IPU_MMU_MAX_TLB_L2_STREAMS	40U
#define IPU_ZLX_MAX_NUM			32U
#define IPU_ZLX_POOL_NUM		8U
#define IPU_UAO_PLANE_MAX_NUM		64U

/*
 * To maximize the IOSF utlization, IPU need to send requests in bursts.
 * At the DMA interface with the buttress, there are CDC FIFOs with burst
 * collection capability. CDC FIFO burst collectors have a configurable
 * threshold and is configured based on the outcome of performance measurements.
 *
 * isys has 3 ports with IOSF interface for VC0, VC1 and VC2
 * psys has 4 ports with IOSF interface for VC0, VC1w, VC1r and VC2
 *
 * Threshold values are pre-defined and are arrived at after performance
 * evaluations on a type of IPU
 */
#define IPU_MAX_VC_IOSF_PORTS		4

/*
 * IPU must configure correct arbitration mechanism related to the IOSF VC
 * requests. There are two options per VC0 and VC1 - > 0 means rearbitrate on
 * stall and 1 means stall until the request is completed.
 */
#define IPU_BTRS_ARB_MODE_TYPE_REARB	0
#define IPU_BTRS_ARB_MODE_TYPE_STALL	1

/* Currently chosen arbitration mechanism for VC0 */
#define IPU_BTRS_ARB_STALL_MODE_VC0	IPU_BTRS_ARB_MODE_TYPE_REARB

/* Currently chosen arbitration mechanism for VC1 */
#define IPU_BTRS_ARB_STALL_MODE_VC1	IPU_BTRS_ARB_MODE_TYPE_REARB

/* One L2 entry maps 1024 L1 entries and one L1 entry per page */
#define IPU_MMUV2_L2_RANGE		(1024 * PAGE_SIZE)
/* Max L2 blocks per stream */
#define IPU_MMUV2_MAX_L2_BLOCKS		2
/* Max L1 blocks per stream */
#define IPU_MMUV2_MAX_L1_BLOCKS		16
#define IPU_MMUV2_TRASH_RANGE		(IPU_MMUV2_L2_RANGE *	\
					 IPU_MMUV2_MAX_L2_BLOCKS)
/* Entries per L1 block */
#define MMUV2_ENTRIES_PER_L1_BLOCK	16
#define MMUV2_TRASH_L1_BLOCK_OFFSET	(MMUV2_ENTRIES_PER_L1_BLOCK * PAGE_SIZE)
#define MMUV2_TRASH_L2_BLOCK_OFFSET	IPU_MMUV2_L2_RANGE

struct ipu7_mmu_hw {
	char name[32];

Annotation

Implementation Notes