drivers/staging/media/ipu7/ipu7-isys.c

Source file repositories/reference/linux-study-clean/drivers/staging/media/ipu7/ipu7-isys.c

File Facts

System
Linux kernel
Corpus path
drivers/staging/media/ipu7/ipu7-isys.c
Extension
.c
Size
30459 bytes
Lines
1167
Domain
Driver Families
Bucket
drivers/staging
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ipu7_csi2_error {
	const char *error_string;
	bool is_info_only;
};

/*
 * Strings corresponding to CSI-2 receiver errors are here.
 * Corresponding macros are defined in the header file.
 */
static const struct ipu7_csi2_error dphy_rx_errors[] = {
	{ "Error handler FIFO full", false },
	{ "Reserved Short Packet encoding detected", true },
	{ "Reserved Long Packet encoding detected", true },
	{ "Received packet is too short", false},
	{ "Received packet is too long", false},
	{ "Short packet discarded due to errors", false },
	{ "Long packet discarded due to errors", false },
	{ "CSI Combo Rx interrupt", false },
	{ "IDI CDC FIFO overflow(remaining bits are reserved as 0)", false },
	{ "Received NULL packet", true },
	{ "Received blanking packet", true },
	{ "Tie to 0", true },
	{ }
};

static void ipu7_isys_register_errors(struct ipu7_isys_csi2 *csi2)
{
	u32 offset = IS_IO_CSI2_ERR_LEGACY_IRQ_CTL_BASE(csi2->port);
	u32 status = readl(csi2->base + offset + IRQ_CTL_STATUS);
	u32 mask = IPU7_CSI_RX_ERROR_IRQ_MASK;

	if (!status)
		return;

	dev_dbg(&csi2->isys->adev->auxdev.dev, "csi2-%u error status 0x%08x\n",
		csi2->port, status);

	writel(status & mask, csi2->base + offset + IRQ_CTL_CLEAR);
	csi2->receiver_errors |= status & mask;
}

static void ipu7_isys_csi2_error(struct ipu7_isys_csi2 *csi2)
{
	struct ipu7_csi2_error const *errors;
	unsigned int i;
	u32 status;

	/* Register errors once more in case of error interrupts are disabled */
	ipu7_isys_register_errors(csi2);
	status = csi2->receiver_errors;
	csi2->receiver_errors = 0;
	errors = dphy_rx_errors;

	for (i = 0; i < CSI_RX_NUM_ERRORS_IN_IRQ; i++) {
		if (status & BIT(i))
			dev_err_ratelimited(&csi2->isys->adev->auxdev.dev,
					    "csi2-%i error: %s\n",
					    csi2->port,
					    errors[i].error_string);
	}
}

struct resp_to_msg {
	enum ipu7_insys_resp_type type;
	const char *msg;
};

static const struct resp_to_msg is_fw_msg[] = {
	{IPU_INSYS_RESP_TYPE_STREAM_OPEN_DONE,
	 "IPU_INSYS_RESP_TYPE_STREAM_OPEN_DONE"},
	{IPU_INSYS_RESP_TYPE_STREAM_START_AND_CAPTURE_ACK,
	 "IPU_INSYS_RESP_TYPE_STREAM_START_AND_CAPTURE_ACK"},
	{IPU_INSYS_RESP_TYPE_STREAM_CAPTURE_ACK,
	 "IPU_INSYS_RESP_TYPE_STREAM_CAPTURE_ACK"},
	{IPU_INSYS_RESP_TYPE_STREAM_ABORT_ACK,
	 "IPU_INSYS_RESP_TYPE_STREAM_ABORT_ACK"},
	{IPU_INSYS_RESP_TYPE_STREAM_FLUSH_ACK,
	 "IPU_INSYS_RESP_TYPE_STREAM_FLUSH_ACK"},
	{IPU_INSYS_RESP_TYPE_STREAM_CLOSE_ACK,
	 "IPU_INSYS_RESP_TYPE_STREAM_CLOSE_ACK"},
	{IPU_INSYS_RESP_TYPE_PIN_DATA_READY,
	 "IPU_INSYS_RESP_TYPE_PIN_DATA_READY"},
	{IPU_INSYS_RESP_TYPE_FRAME_SOF, "IPU_INSYS_RESP_TYPE_FRAME_SOF"},
	{IPU_INSYS_RESP_TYPE_FRAME_EOF, "IPU_INSYS_RESP_TYPE_FRAME_EOF"},
	{IPU_INSYS_RESP_TYPE_STREAM_START_AND_CAPTURE_DONE,
	 "IPU_INSYS_RESP_TYPE_STREAM_START_AND_CAPTURE_DONE"},
	{IPU_INSYS_RESP_TYPE_STREAM_CAPTURE_DONE,
	 "IPU_INSYS_RESP_TYPE_STREAM_CAPTURE_DONE"},
	{N_IPU_INSYS_RESP_TYPE, "N_IPU_INSYS_RESP_TYPE"},
};

Annotation

Implementation Notes