drivers/staging/media/ipu7/ipu7-isys-csi2-regs.h

Source file repositories/reference/linux-study-clean/drivers/staging/media/ipu7/ipu7-isys-csi2-regs.h

File Facts

System: Linux kernel
Corpus path: drivers/staging/media/ipu7/ipu7-isys-csi2-regs.h
Extension: .h
Size: 51998 bytes
Lines: 1198
Domain: Driver Families
Bucket: drivers/staging
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

enum CSI_FE_MODE_TYPE
enum CSI_FE_INPUT_MODE
enum MGC_CSI_ADPL_TYPE
enum CSI2HOST_SELECTION

Annotated Snippet

#ifndef IPU7_ISYS_CSI2_REG_H
#define IPU7_ISYS_CSI2_REG_H

/* IS main regs base */
#define IS_MAIN_BASE				0x240000
#define IS_MAIN_S2B_BASE			(IS_MAIN_BASE + 0x22000)
#define IS_MAIN_B2O_BASE			(IS_MAIN_BASE + 0x26000)
#define IS_MAIN_ISD_M0_BASE			(IS_MAIN_BASE + 0x2b000)
#define IS_MAIN_ISD_M1_BASE			(IS_MAIN_BASE + 0x2b100)
#define IS_MAIN_ISD_INT_BASE			(IS_MAIN_BASE + 0x2b200)
#define IS_MAIN_GDA_BASE			(IS_MAIN_BASE + 0x32000)
#define IS_MAIN_GPREGS_MAIN_BASE		(IS_MAIN_BASE + 0x32500)
#define IS_MAIN_IRQ_CTRL_BASE			(IS_MAIN_BASE + 0x32700)
#define IS_MAIN_PWM_CTRL_BASE			(IS_MAIN_BASE + 0x32b00)

#define S2B_IRQ_COMMON_0_CTL_STATUS		(IS_MAIN_S2B_BASE + 0x1c)
#define S2B_IRQ_COMMON_0_CTL_CLEAR		(IS_MAIN_S2B_BASE + 0x20)
#define S2B_IRQ_COMMON_0_CTL_ENABLE		(IS_MAIN_S2B_BASE + 0x24)
#define S2B_IID_IRQ_CTL_STATUS(iid)		(IS_MAIN_S2B_BASE + 0x94 + \
						 0x100 * (iid))

#define B2O_IRQ_COMMON_0_CTL_STATUS		(IS_MAIN_B2O_BASE + 0x30)
#define B2O_IRQ_COMMON_0_CTL_CLEAR		(IS_MAIN_B2O_BASE + 0x34)
#define B2O_IRQ_COMMON_0_CTL_ENABLE		(IS_MAIN_B2O_BASE + 0x38)
#define B2O_IID_IRQ_CTL_STATUS(oid)		(IS_MAIN_B2O_BASE + 0x3dc + \
						 0x200 * (oid))

#define ISD_M0_IRQ_CTL_STATUS			(IS_MAIN_ISD_M0_BASE + 0x1c)
#define ISD_M0_IRQ_CTL_CLEAR			(IS_MAIN_ISD_M0_BASE + 0x20)
#define ISD_M0_IRQ_CTL_ENABLE			(IS_MAIN_ISD_M0_BASE + 0x24)

#define ISD_M1_IRQ_CTL_STATUS			(IS_MAIN_ISD_M1_BASE + 0x1c)
#define ISD_M1_IRQ_CTL_CLEAR			(IS_MAIN_ISD_M1_BASE + 0x20)
#define ISD_M1_IRQ_CTL_ENABLE			(IS_MAIN_ISD_M1_BASE + 0x24)

#define ISD_INT_IRQ_CTL_STATUS			(IS_MAIN_ISD_INT_BASE + 0x1c)
#define ISD_INT_IRQ_CTL_CLEAR			(IS_MAIN_ISD_INT_BASE + 0x20)
#define ISD_INT_IRQ_CTL_ENABLE			(IS_MAIN_ISD_INT_BASE + 0x24)

#define GDA_IRQ_CTL_STATUS			(IS_MAIN_GDA_BASE + 0x1c)
#define GDA_IRQ_CTL_CLEAR			(IS_MAIN_GDA_BASE + 0x20)
#define GDA_IRQ_CTL_ENABLE			(IS_MAIN_GDA_BASE + 0x24)

#define IS_MAIN_IRQ_CTL_EDGE			IS_MAIN_IRQ_CTRL_BASE
#define IS_MAIN_IRQ_CTL_MASK			(IS_MAIN_IRQ_CTRL_BASE + 0x4)
#define IS_MAIN_IRQ_CTL_STATUS			(IS_MAIN_IRQ_CTRL_BASE + 0x8)
#define IS_MAIN_IRQ_CTL_CLEAR			(IS_MAIN_IRQ_CTRL_BASE + 0xc)
#define IS_MAIN_IRQ_CTL_ENABLE			(IS_MAIN_IRQ_CTRL_BASE + 0x10)
#define IS_MAIN_IRQ_CTL_LEVEL_NOT_PULSE		(IS_MAIN_IRQ_CTRL_BASE + 0x14)

/* IS IO regs base */
#define IS_PHY_NUM				4U
#define IS_IO_BASE				0x280000

/* dwc csi cdphy registers */
#define IS_IO_CDPHY_BASE(i)			(IS_IO_BASE + 0x10000 * (i))
#define PPI_STARTUP_RW_COMMON_DPHY_0			0x1800
#define PPI_STARTUP_RW_COMMON_DPHY_1			0x1802
#define PPI_STARTUP_RW_COMMON_DPHY_2			0x1804
#define PPI_STARTUP_RW_COMMON_DPHY_3			0x1806
#define PPI_STARTUP_RW_COMMON_DPHY_4			0x1808
#define PPI_STARTUP_RW_COMMON_DPHY_5			0x180a
#define PPI_STARTUP_RW_COMMON_DPHY_6			0x180c
#define PPI_STARTUP_RW_COMMON_DPHY_7			0x180e
#define PPI_STARTUP_RW_COMMON_DPHY_8			0x1810
#define PPI_STARTUP_RW_COMMON_DPHY_9			0x1812
#define PPI_STARTUP_RW_COMMON_DPHY_A			0x1814
#define PPI_STARTUP_RW_COMMON_DPHY_10			0x1820
#define PPI_STARTUP_RW_COMMON_STARTUP_1_1		0x1822
#define PPI_STARTUP_RW_COMMON_STARTUP_1_2		0x1824
#define PPI_CALIBCTRL_RW_COMMON_CALIBCTRL_2_0		0x1840
#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_1		0x1842
#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_2		0x1844
#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_3		0x1846
#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_4		0x1848
#define PPI_CALIBCTRL_R_COMMON_CALIBCTRL_2_5		0x184a
#define PPI_CALIBCTRL_RW_COMMON_BG_0			0x184c
#define PPI_CALIBCTRL_RW_COMMON_CALIBCTRL_2_7		0x184e
#define PPI_CALIBCTRL_RW_ADC_CFG_0			0x1850
#define PPI_CALIBCTRL_RW_ADC_CFG_1			0x1852
#define PPI_CALIBCTRL_R_ADC_DEBUG			0x1854
#define PPI_RW_LPDCOCAL_TOP_OVERRIDE			0x1c00
#define PPI_RW_LPDCOCAL_TIMEBASE			0x1c02
#define PPI_RW_LPDCOCAL_NREF				0x1c04
#define PPI_RW_LPDCOCAL_NREF_RANGE			0x1c06
#define PPI_RW_LPDCOCAL_NREF_TRIGGER_MAN		0x1c08
#define PPI_RW_LPDCOCAL_TWAIT_CONFIG			0x1c0a
#define PPI_RW_LPDCOCAL_VT_CONFIG			0x1c0c
#define PPI_R_LPDCOCAL_DEBUG_RB				0x1c0e
#define PPI_RW_LPDCOCAL_COARSE_CFG			0x1c10

Annotation

Detected declarations: `enum CSI_FE_MODE_TYPE`, `enum CSI_FE_INPUT_MODE`, `enum MGC_CSI_ADPL_TYPE`, `enum CSI2HOST_SELECTION`.
Atlas domain: Driver Families / drivers/staging.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.