drivers/staging/media/meson/vdec/codec_hevc_common.c
Source file repositories/reference/linux-study-clean/drivers/staging/media/meson/vdec/codec_hevc_common.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/staging/media/meson/vdec/codec_hevc_common.c- Extension
.c- Size
- 8451 bytes
- Lines
- 298
- Domain
- Driver Families
- Bucket
- drivers/staging
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
media/v4l2-mem2mem.hmedia/videobuf2-dma-contig.hcodec_hevc_common.hvdec_helpers.hhevc_regs.h
Detected Declarations
function codec_hevc_setup_decode_headfunction codec_hevc_setup_buffers_gxbbfunction v4l2_m2m_for_each_dst_buffunction codec_hevc_setup_buffers_gxlfunction v4l2_m2m_for_each_dst_buffunction codec_hevc_free_fbc_buffersfunction codec_hevc_alloc_fbc_buffersfunction v4l2_m2m_for_each_dst_buffunction codec_hevc_free_mmu_headersfunction codec_hevc_alloc_mmu_headersfunction v4l2_m2m_for_each_dst_buffunction codec_hevc_setup_buffersfunction codec_hevc_fill_mmu_mapexport codec_hevc_setup_decode_headexport codec_hevc_free_fbc_buffersexport codec_hevc_free_mmu_headersexport codec_hevc_setup_buffersexport codec_hevc_fill_mmu_map
Annotated Snippet
if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) {
val = buf_y_paddr | (idx << 8) | 1;
amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
val);
} else {
buf_uv_paddr = vb2_dma_contig_plane_dma_addr(vb, 1);
val = buf_y_paddr | ((idx * 2) << 8) | 1;
amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
val);
val = buf_uv_paddr | ((idx * 2 + 1) << 8) | 1;
amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
val);
}
}
if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit))
val = buf_y_paddr | (idx << 8) | 1;
else
val = buf_y_paddr | ((idx * 2) << 8) | 1;
/* Fill the remaining unused slots with the last buffer's Y addr */
for (i = buf_num; i < MAX_REF_PIC_NUM; ++i)
amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, val);
amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 1);
amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
for (i = 0; i < 32; ++i)
amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
}
static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
struct codec_hevc_common *comm,
int is_10bit)
{
struct amvdec_core *core = sess->core;
struct v4l2_m2m_buffer *buf;
u32 revision = core->platform->revision;
u32 pixfmt_cap = sess->pixfmt_cap;
int i;
amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
BIT(2) | BIT(1));
v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
struct vb2_buffer *vb = &buf->vb.vb2_buf;
dma_addr_t buf_y_paddr = 0;
dma_addr_t buf_uv_paddr = 0;
u32 idx = vb->index;
if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
buf_y_paddr = comm->mmu_header_paddr[idx];
else if (codec_hevc_use_downsample(pixfmt_cap, is_10bit))
buf_y_paddr = comm->fbc_buffer_paddr[idx];
else
buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
buf_y_paddr >> 5);
if (!codec_hevc_use_fbc(pixfmt_cap, is_10bit)) {
buf_uv_paddr = vb2_dma_contig_plane_dma_addr(vb, 1);
amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
buf_uv_paddr >> 5);
}
}
amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 1);
amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
for (i = 0; i < 32; ++i)
amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
}
void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
struct codec_hevc_common *comm)
{
struct device *dev = sess->core->dev;
u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
int i;
for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
if (comm->fbc_buffer_vaddr[i]) {
dma_free_coherent(dev, am21_size,
comm->fbc_buffer_vaddr[i],
comm->fbc_buffer_paddr[i]);
comm->fbc_buffer_vaddr[i] = NULL;
}
}
}
EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
Annotation
- Immediate include surface: `media/v4l2-mem2mem.h`, `media/videobuf2-dma-contig.h`, `codec_hevc_common.h`, `vdec_helpers.h`, `hevc_regs.h`.
- Detected declarations: `function codec_hevc_setup_decode_head`, `function codec_hevc_setup_buffers_gxbb`, `function v4l2_m2m_for_each_dst_buf`, `function codec_hevc_setup_buffers_gxl`, `function v4l2_m2m_for_each_dst_buf`, `function codec_hevc_free_fbc_buffers`, `function codec_hevc_alloc_fbc_buffers`, `function v4l2_m2m_for_each_dst_buf`, `function codec_hevc_free_mmu_headers`, `function codec_hevc_alloc_mmu_headers`.
- Atlas domain: Driver Families / drivers/staging.
- Implementation status: integration implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.