drivers/staging/media/sunxi/cedrus/cedrus_regs.h

Source file repositories/reference/linux-study-clean/drivers/staging/media/sunxi/cedrus/cedrus_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/staging/media/sunxi/cedrus/cedrus_regs.h
Extension
.h
Size
28986 bytes
Lines
718
Domain
Driver Families
Bucket
drivers/staging
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _CEDRUS_REGS_H_
#define _CEDRUS_REGS_H_

#define SHIFT_AND_MASK_BITS(v, h, l) \
	(((unsigned long)(v) << (l)) & GENMASK(h, l))

/*
 * Common acronyms and contractions used in register descriptions:
 * * VLD : Variable-Length Decoder
 * * IQ: Inverse Quantization
 * * IDCT: Inverse Discrete Cosine Transform
 * * MC: Motion Compensation
 * * STCD: Start Code Detect
 * * SDRT: Scale Down and Rotate
 * * WB: Writeback
 * * BITS/BS: Bitstream
 * * MB: Macroblock
 * * CTU: Coding Tree Unit
 * * CTB: Coding Tree Block
 * * IDX: Index
 */

#define VE_ENGINE_DEC_MPEG			0x100
#define VE_ENGINE_DEC_H264			0x200
#define VE_ENGINE_DEC_H265			0x500

#define VE_MODE					0x00

#define VE_MODE_PIC_WIDTH_IS_4096		BIT(22)
#define VE_MODE_PIC_WIDTH_MORE_2048		BIT(21)
#define VE_MODE_REC_WR_MODE_2MB			(0x01 << 20)
#define VE_MODE_REC_WR_MODE_1MB			(0x00 << 20)
#define VE_MODE_DDR_MODE_BW_128			(0x03 << 16)
#define VE_MODE_DDR_MODE_BW_256			(0x02 << 16)
#define VE_MODE_DISABLED			(0x07 << 0)
#define VE_MODE_DEC_H265			(0x04 << 0)
#define VE_MODE_DEC_H264			(0x01 << 0)
#define VE_MODE_DEC_MPEG			(0x00 << 0)

#define VE_BUF_CTRL				0x50

#define VE_BUF_CTRL_INTRAPRED_EXT_RAM		(0x02 << 2)
#define VE_BUF_CTRL_INTRAPRED_MIXED_RAM		(0x01 << 2)
#define VE_BUF_CTRL_INTRAPRED_INT_SRAM		(0x00 << 2)
#define VE_BUF_CTRL_DBLK_EXT_RAM		(0x02 << 0)
#define VE_BUF_CTRL_DBLK_MIXED_RAM		(0x01 << 0)
#define VE_BUF_CTRL_DBLK_INT_SRAM		(0x00 << 0)

#define VE_DBLK_DRAM_BUF_ADDR			0x54
#define VE_INTRAPRED_DRAM_BUF_ADDR		0x58
#define VE_PRIMARY_CHROMA_BUF_LEN		0xc4
#define VE_PRIMARY_FB_LINE_STRIDE		0xc8

#define VE_PRIMARY_FB_LINE_STRIDE_CHROMA(s)	SHIFT_AND_MASK_BITS(s, 31, 16)
#define VE_PRIMARY_FB_LINE_STRIDE_LUMA(s)	SHIFT_AND_MASK_BITS(s, 15, 0)

#define VE_CHROMA_BUF_LEN			0xe8

#define VE_SECONDARY_OUT_FMT_TILED_32_NV12	(0x00 << 30)
#define VE_SECONDARY_OUT_FMT_EXT		(0x01 << 30)
#define VE_SECONDARY_OUT_FMT_YU12		(0x02 << 30)
#define VE_SECONDARY_OUT_FMT_YV12		(0x03 << 30)
#define VE_CHROMA_BUF_LEN_SDRT(l)		SHIFT_AND_MASK_BITS(l, 27, 0)

#define VE_PRIMARY_OUT_FMT			0xec

#define VE_PRIMARY_OUT_FMT_TILED_32_NV12	(0x00 << 4)
#define VE_PRIMARY_OUT_FMT_TILED_128_NV12	(0x01 << 4)
#define VE_PRIMARY_OUT_FMT_YU12			(0x02 << 4)
#define VE_PRIMARY_OUT_FMT_YV12			(0x03 << 4)
#define VE_PRIMARY_OUT_FMT_NV12			(0x04 << 4)
#define VE_PRIMARY_OUT_FMT_NV21			(0x05 << 4)
#define VE_SECONDARY_OUT_FMT_EXT_TILED_32_NV12	(0x00 << 0)
#define VE_SECONDARY_OUT_FMT_EXT_TILED_128_NV12	(0x01 << 0)
#define VE_SECONDARY_OUT_FMT_EXT_YU12		(0x02 << 0)
#define VE_SECONDARY_OUT_FMT_EXT_YV12		(0x03 << 0)
#define VE_SECONDARY_OUT_FMT_EXT_NV12		(0x04 << 0)
#define VE_SECONDARY_OUT_FMT_EXT_NV21		(0x05 << 0)

#define VE_VERSION				0xf0

#define VE_VERSION_SHIFT			16

#define VE_DEC_MPEG_MP12HDR			(VE_ENGINE_DEC_MPEG + 0x00)

#define VE_DEC_MPEG_MP12HDR_SLICE_TYPE(t)	SHIFT_AND_MASK_BITS(t, 30, 28)
#define VE_DEC_MPEG_MP12HDR_F_CODE_SHIFT(x, y)	(24 - 4 * (y) - 8 * (x))
#define VE_DEC_MPEG_MP12HDR_F_CODE(__x, __y, __v) \
	(((unsigned long)(__v) & GENMASK(3, 0)) << VE_DEC_MPEG_MP12HDR_F_CODE_SHIFT(__x, __y))

Annotation

Implementation Notes