drivers/staging/most/dim2/reg.h

Source file repositories/reference/linux-study-clean/drivers/staging/most/dim2/reg.h

File Facts

System
Linux kernel
Corpus path
drivers/staging/most/dim2/reg.h
Extension
.h
Size
3256 bytes
Lines
158
Domain
Driver Families
Bucket
drivers/staging
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dim2_regs {
	u32 MLBC0;       /* 0x00 */
	u32 rsvd0[1];    /* 0x01 */
	u32 MLBPC0;      /* 0x02 */
	u32 MS0;         /* 0x03 */
	u32 rsvd1[1];    /* 0x04 */
	u32 MS1;         /* 0x05 */
	u32 rsvd2[2];    /* 0x06 */
	u32 MSS;         /* 0x08 */
	u32 MSD;         /* 0x09 */
	u32 rsvd3[1];    /* 0x0A */
	u32 MIEN;        /* 0x0B */
	u32 rsvd4[1];    /* 0x0C */
	u32 MLBPC2;      /* 0x0D */
	u32 MLBPC1;      /* 0x0E */
	u32 MLBC1;       /* 0x0F */
	u32 rsvd5[0x10]; /* 0x10 */
	u32 HCTL;        /* 0x20 */
	u32 rsvd6[1];    /* 0x21 */
	u32 HCMR0;       /* 0x22 */
	u32 HCMR1;       /* 0x23 */
	u32 HCER0;       /* 0x24 */
	u32 HCER1;       /* 0x25 */
	u32 HCBR0;       /* 0x26 */
	u32 HCBR1;       /* 0x27 */
	u32 rsvd7[8];    /* 0x28 */
	u32 MDAT0;       /* 0x30 */
	u32 MDAT1;       /* 0x31 */
	u32 MDAT2;       /* 0x32 */
	u32 MDAT3;       /* 0x33 */
	u32 MDWE0;       /* 0x34 */
	u32 MDWE1;       /* 0x35 */
	u32 MDWE2;       /* 0x36 */
	u32 MDWE3;       /* 0x37 */
	u32 MCTL;        /* 0x38 */
	u32 MADR;        /* 0x39 */
	u32 rsvd8[0xb6]; /* 0x3A */
	u32 ACTL;        /* 0xF0 */
	u32 rsvd9[3];    /* 0xF1 */
	u32 ACSR0;       /* 0xF4 */
	u32 ACSR1;       /* 0xF5 */
	u32 ACMR0;       /* 0xF6 */
	u32 ACMR1;       /* 0xF7 */
};

#define DIM2_MASK(n)  (~((~(u32)0) << (n)))

enum {
	MLBC0_MLBLK_BIT = 7,

	MLBC0_MLBPEN_BIT = 5,

	MLBC0_MLBCLK_SHIFT = 2,
	MLBC0_MLBCLK_VAL_256FS = 0,
	MLBC0_MLBCLK_VAL_512FS = 1,
	MLBC0_MLBCLK_VAL_1024FS = 2,
	MLBC0_MLBCLK_VAL_2048FS = 3,

	MLBC0_FCNT_SHIFT = 15,
	MLBC0_FCNT_MASK = 7,
	MLBC0_FCNT_MAX_VAL = 6,

	MLBC0_MLBEN_BIT = 0,

	MIEN_CTX_BREAK_BIT = 29,
	MIEN_CTX_PE_BIT = 28,
	MIEN_CTX_DONE_BIT = 27,

	MIEN_CRX_BREAK_BIT = 26,
	MIEN_CRX_PE_BIT = 25,
	MIEN_CRX_DONE_BIT = 24,

	MIEN_ATX_BREAK_BIT = 22,
	MIEN_ATX_PE_BIT = 21,
	MIEN_ATX_DONE_BIT = 20,

	MIEN_ARX_BREAK_BIT = 19,
	MIEN_ARX_PE_BIT = 18,
	MIEN_ARX_DONE_BIT = 17,

	MIEN_SYNC_PE_BIT = 16,

	MIEN_ISOC_BUFO_BIT = 1,
	MIEN_ISOC_PE_BIT = 0,

	MLBC1_NDA_SHIFT = 8,
	MLBC1_NDA_MASK = 0xFF,

	MLBC1_CLKMERR_BIT = 7,
	MLBC1_LOCKERR_BIT = 6,

Annotation

Implementation Notes