drivers/staging/rtl8723bs/include/Hal8192CPhyReg.h

Source file repositories/reference/linux-study-clean/drivers/staging/rtl8723bs/include/Hal8192CPhyReg.h

File Facts

System
Linux kernel
Corpus path
drivers/staging/rtl8723bs/include/Hal8192CPhyReg.h
Extension
.h
Size
6467 bytes
Lines
233
Domain
Driver Families
Bucket
drivers/staging
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __INC_HAL8192CPHYREG_H
#define __INC_HAL8192CPHYREG_H


/*--------------------------Define Parameters-------------------------------*/

/*  */
/*        8192S Register offset definition */
/*  */

/*  */
/*  BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
/*  1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */
/*  2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
/*  3. RF register 0x00-2E */
/*  4. Bit Mask for BB/RF register */
/*  5. Other definition for BB/RF R/W */
/*  */

/*  */
/*  3. Page8(0x800) */
/*  */
#define		rFPGA0_RFMOD				0x800	/* RF mode & CCK TxSC  RF BW Setting?? */

#define		rFPGA0_XA_HSSIParameter1		0x820	/*  RF 3 wire register */
#define		rFPGA0_XA_HSSIParameter2		0x824
#define		rFPGA0_XB_HSSIParameter1		0x828
#define		rFPGA0_XB_HSSIParameter2		0x82c
#define		rTxAGC_B_Rate18_06				0x830
#define		rTxAGC_B_Rate54_24				0x834
#define		rTxAGC_B_CCK1_55_Mcs32		0x838
#define		rTxAGC_B_Mcs03_Mcs00			0x83c

#define		rTxAGC_B_Mcs07_Mcs04			0x848

#define		rFPGA0_XA_LSSIParameter		0x840
#define		rFPGA0_XB_LSSIParameter		0x844

#define		rFPGA0_XCD_SwitchControl		0x85c

#define		rFPGA0_XA_RFInterfaceOE		0x860	/*  RF Channel switch */
#define		rFPGA0_XB_RFInterfaceOE		0x864

#define		rTxAGC_B_CCK11_A_CCK2_11		0x86c

#define		rFPGA0_XAB_RFInterfaceSW		0x870	/*  RF Interface Software Control */
#define		rFPGA0_XCD_RFInterfaceSW		0x874

#define		rFPGA0_XA_LSSIReadBack		0x8a0	/*  Transceiver LSSI Readback */
#define		rFPGA0_XB_LSSIReadBack		0x8a4

#define		TransceiverA_HSPI_Readback	0x8b8	/*  Transceiver A HSPI Readback */
#define		TransceiverB_HSPI_Readback	0x8bc	/*  Transceiver B HSPI Readback */

/*  */
/*  4. Page9(0x900) */
/*  */
#define		rFPGA1_RFMOD				0x900	/* RF mode & OFDM TxSC  RF BW Setting?? */

#define		rS0S1_PathSwitch			0x948

/*  */
/*  5. PageA(0xA00) */
/*  */
/*  Set Control channel to upper or lower. These settings are required only for 40MHz */
#define		rCCK0_System				0xa00

#define		rCCK0_AFESetting			0xa04	/*  Disable init gain now Select RX path by RSSI */

/*  */
/*  PageB(0xB00) */
/*  */
#define		rConfig_AntA				0xb68
#define		rConfig_AntB				0xb6c

/*  */
/*  6. PageC(0xC00) */
/*  */
#define		rOFDM0_TRxPathEnable		0xc04
#define		rOFDM0_TRMuxPar			0xc08

#define		rOFDM0_XARxIQImbalance		0xc14  /* RxIQ imbalance matrix */
#define		rOFDM0_XBRxIQImbalance		0xc1c

#define		rOFDM0_RxDSP				0xc40  /* Rx Sync Path */
#define		rOFDM0_ECCAThreshold		0xc4c /*  energy CCA */

#define		rOFDM0_AGCRSSITable			0xc78

#define		rOFDM0_XATxIQImbalance		0xc80	/*  TX PWR TRACK and DIG */

Annotation

Implementation Notes